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RF-Interconnect for Future Network-On-Chip

  • Sai-Wang Tam
  • Eran Socher
  • Mau-Chung Frank Chang
  • Jason Cong
  • Glenn D. Reinman
Chapter

Abstract

In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). It is projected that communication via NoC is one of the primary limiters to both performance and power consumption. To mitigate such problems, we explore the use of multiband RF-interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission and reconfigurable bandwidth. At the same time, we investigate the CMOS mixed-signal circuit implementation challenges for improving the RF-I signaling integrity and efficiency. Furthermore, we propose a micro-architectural framework that can be used to facilitate the exploration of scalable low power NoC architectures based on physical planning and prototyping.

Keywords

Transmission Line Transactional Memory Power Supply Noise Multiple Frequency Band Baseband Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

The authors would like to thank the US DARPA and GSRC for their contract supports and TAPO/IBM for their foundry service.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Sai-Wang Tam
    • 1
  • Eran Socher
  • Mau-Chung Frank Chang
  • Jason Cong
  • Glenn D. Reinman
  1. 1.Electrical Engineering DepartmentUniversity of California, Los AngelesLos AngelesUSA

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