Advertisement

System Exploration

  • Jari Kreku
  • Kari Tiensyrjä
Chapter

Abstract

Future embedded system products, e.g. smart handheld mobile terminals, will accommodate a large number of applications that will partly run sequentially and independently, partly concurrently and interacting on massively parallel computing platforms. Already for systems of moderate complexity, the design space will be huge and its exploration requires that the system architect is able to quickly evaluate the performances of candidate architectures and application mappings. The mainstream evaluation technique today is the system-level performance simulation of the applications and platforms using abstracted workload and processing capacity models, respectively. These virtual system models allow fast simulation of large systems at an early phase of development with reasonable modelling effort and time. The accuracy of the performance results is dependent on how closely the models used reflect the actual system. This chapter gives a description of the ABSOLUT modelling and simulation approach. Firstly, it gives an outline view of the approach and its evolution. Secondly, it describes how to create different models. Thirdly, it describes the means for simulation.

References

  1. 1.
    L. Benini, A. Bogliolo, and G. DeMicheli. A survey of design techniques for system-level dynamic power management. IEEE TVSLI, 8(3):299–316, 2000.Google Scholar
  2. 2.
    L. Benini, R. Hodgson, and P. Siegel. System-level power estimation and optimization. In International Symposium on Low Power Electronics and Design, 1998.Google Scholar
  3. 3.
    M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti. System-level power analysis methodology applied to the amba ahb bus. In The Design Automation and Test in Europe (DATE), 2003.Google Scholar
  4. 4.
    E.A. de Kock, G. Essink, W.J.M. Smits, P. van der Wolf, J.-Y. Brunel, W.M. Kruijtzer, P. Lieverse, and K.A. Vissers. YAPI: Application modeling for signal processing systems. In 37th Design Automation Conference (DAC), pages 402–405, 2000.Google Scholar
  5. 5.
    N. Dhanwada, I.C. Lin, and V. Narayanan. A power estimation methodology for SystemC transaction level models. In ACM Proceedings of CODES+ISSS05, pages 142–147, September 2005.Google Scholar
  6. 6.
    K. Flautner, D. Flynn, D. Roberts, and D.I. Patel. IEM926: An energy efficient SoC with dynamic voltage scaling. In The Design Automation and Test in Europe (DATE), 2004.Google Scholar
  7. 7.
    D. Gajski, J. Zhu, R. Dörner, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Methodology. Kluwer Academic Publishers, 2000. 313 p.Google Scholar
  8. 8.
    F. Ghenassia, editor. Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer, 2005. 271 p.Google Scholar
  9. 9.
    M. Gries. Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal, 38(2):131–183, 2004.CrossRefGoogle Scholar
  10. 10.
    S. Idgunji. Case study of a low power MTCMOS based ARM926 SoC: Design, analysis and test challenges. In IEEE International Test Conference (ITC), pages 1–10, October 2007.Google Scholar
  11. 11.
    R. Jain. The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling. John Wiley & Sons, Inc., 1991. 685 p.Google Scholar
  12. 12.
    T. Kangas, P. Kukkala, H. Orsila, E. Salminen, M. Hännikäinen, T.D. Hämäläinen, J. Riihimäki, and K. Kuusilinna. UML-based multi-processor SoC design framework. Transactions on Embedded Computing Systems, 5(2):281–320, 2006.CrossRefGoogle Scholar
  13. 13.
    J. Kreku, M. Eteläperä, and J-P. Soininen. Exploitation of UML 2.0-based platform service model and SystemC workload simulation in MPEG-4 partitioning. In International Symposium on System-on-Chip Proceedings, pages 167–170, 2005.Google Scholar
  14. 14.
    J. Kreku, M. Hoppari, T. Kestilä, Y. Qu, J.-P. Soininen, and K. Tiensyrjä. Languages for Embedded Systems and their Applications, volume 36 of Lecture Notes in Electrical Engineering, chapter Application Workload and SystemC Platform Modeling for Performance Evaluation, pages 131–148. Springer, 2009.Google Scholar
  15. 15.
    J. Kreku, M. Hoppari, T. Kestilä, Yang Qu, J.-P. Soininen, P. Andersson, and K. Tiensyrjä. Combining uml2 application and systemc platform modelling for performance evaluation of real-time embedded systems. EURASIP Journal on Embedded Systems, 2008.Google Scholar
  16. 16.
    J. Kreku, M. Hoppari, K. Tiensyrjä, and P. Andersson. Systemc workload model generation from uml for performance simulation. In Forum on Specification and Design Languages, 2007.Google Scholar
  17. 17.
    J. Kreku, T. Kauppi, and J-P. Soininen. Evaluation of platform architecture performance using abstract instruction-level workload models. In International Symposium on System-on-Chip Proceedings, pages 43–48, 2004.Google Scholar
  18. 18.
    J. Kreku, J. Penttilä, J. Kangas, and J-P. Soininen. Workload simulation method for evaluation of application feasibility in a mobile multiprocessor platform. In Proceedings of the Euromicro Symposium on Digital System Design, pages 532–539, 2004.Google Scholar
  19. 19.
    J. Kreku, Y. Qu, J.-P. Soininen, and K. Tiensyrjä. Layered uml workload and systemc platform models for performance simulation. In International Forum on Specification and Design Languages (FDL), pages 223–228, 2006.Google Scholar
  20. 20.
    J. Kreku, K. Tiensyrjä, and G. Vanmeerbeeck. Automatic workload generation for system-level exploration based on modified gcc compiler. In Design, Automation and Test in Europe conference and exhibition, March 2010.Google Scholar
  21. 21.
    K. Lahiri and A. Raghunathan. Power analysis of system-level on-chip communication architectures. In ACM Proceedings of CODES+ISSS04, pages 236–241, September 2004.Google Scholar
  22. 22.
    P. Lieverse, P. van der Wolf, K. Vissers, and E. Deprettere. A methodology for architecture exploration of heterogeneous signal processing systems. Kluwer Journal of VLSI Signal Processing, 29(3):197–207, 2001.MATHCrossRefGoogle Scholar
  23. 23.
    P. Liu, B. Xia, C. Xiang, X. Wang, W. Wang, and Q. Yao. A networks-on-chip architecture design space exploration – the LIB. Computers and Electrical Engineering, (35):817–836, 2009.Google Scholar
  24. 24.
    Micron Technology, Inc. System Power Calculators, 2007. Available at http://micron.com/support/dram/power_calc.html.
  25. 25.
    Micron Technology, Inc. Mobile DRAM Power-Saving Features and Power Calculations, 2009. Available at http://download.micron.com/pdf/technotes/tn4612.pdf.
  26. 26.
    J.-Y. Mignolet, R. Baert, T.J. Ashby, P. Avasare, Hye-On Jang, and Jae Cheol Son. Mpa: Parallelizing an application onto a multicore platform made easy. IEEE Micro, 29(3):31–39, May–June 2009.Google Scholar
  27. 27.
    J. M. Paul, D. E. Thomas, and A. S. Cassidy. High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Transactions on Design Automation of Electronic Systems, 10(3):431–461, July 2005.CrossRefGoogle Scholar
  28. 28.
    A. Pimentel, C. Erbas, and S. Polstra. A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers, 55(2):99–112, 2006.CrossRefGoogle Scholar
  29. 29.
    H. Posadas, F. Herrera, P. Sánchez, E. Villar, and F. Blasco. System-level performance analysis in SystemC. In Proceedings of the Design Automation and Test in Europe Conference, Paris, France, February 2004.Google Scholar
  30. 30.
    S. Thoziyoor, N. Muralimanohar, and N.P. Jouppi. CACTI 5.0. HP Laboratories, 2007. Technical report HPL-2007-167.Google Scholar
  31. 31.
    T. Wild, A. Herkersdorf, and G.-Y. Lee. TAPES — trace-based architecture performance evaluation with SystemC. Design Automation for Embedded Systems, 10(2–3):157–179, 2006. Special Issue on SystemC-based System Modeling, Verification and Synthesis.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.VTT Technical Research Centre of FinlandOuluFinland

Personalised recommendations