Skip to main content

Consequences for Circuit Design and Case Studies

  • Chapter
  • First Online:
  • 1052 Accesses

Abstract

The previous chapters introduced various methods to analyze the influence of variations of the manufacturing process on the performance of devices and circuits. These methods can be applied to evaluate designs for manufacturability. Variations imply negative effects in most cases that shall be reduced. However, there exist also applications where the variations bring an advantage into the design process. The consequences of both aspects regarding special design requirements will be figured out in this chapter.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Notes

  1. 1.

    For more information, see note concerning “Square-Root Law” on page 56.

  2. 2.

    Integral nonlinearity

  3. 3.

    Differential nonlinearity

References

  1. Bowman, K., Duvall, S., Meindl, J.: Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-State Circuits 37(2), 183–190 (2002)

    Article  Google Scholar 

  2. Tschanz, J., Kao, J., Narendra, S.: Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE Journal of Solid-State Circuits 37(11), 1396–1402 (2002)

    Article  Google Scholar 

  3. Taur, Y., Ning, T.: Fundamentals of modern VLSI devices. Cambridge University Press (1998)

    Google Scholar 

  4. Wong, A.K.K.: Resolution Enhancement Techniques in Optical Lithography. SPIE Press (2001)

    Google Scholar 

  5. McCormick, C., Weber, C., Abelson, J., Gates, S.: An amorphous silicon thin film transistor fabricated at 125 C by dc reactive magnetron sputtering. Applied Physics Letters 70, 226 (1997)

    Article  Google Scholar 

  6. Liang, X., Brooks, D.: Mitigating the impact of process variations on processor register files and execution units. In: MICRO 39: Proceedings of the 39th annual ACM/IEEE International Symposium on Microarchitecture (2006)

    Google Scholar 

  7. Tiwari, A., Sarangi, S.R., Torrellas, J.: ReCycle: pipeline adaptation to tolerate process variation. In: ISCA ’07: Proceedings of the 34th annual international symposium on Computer architecture, pp. 323–334 (2007)

    Google Scholar 

  8. Kheterpal, V., Rovner, V., Hersan, T.G., Motiani, D., Takegawa, Y., Strojwas, A.J., Pileggi, L.: Design methodology for ic manufacturability based on regular logic-bricks. In: DAC ’05: Proceedings of the 42nd annual conference on Design automation, pp. 353–358 (2005)

    Google Scholar 

  9. Kobayashi, T., Sakurai, T.: Self-adjusting threshold-voltage scheme (SATS) for low-voltagehigh-speed operation. Proceedings of the IEEE Custom Integrated Circuits Conference (1994)

    Google Scholar 

  10. Razavi, B.: Design of Analog CMOS Integrated Circuits. McGraw-Hill (2001)

    Google Scholar 

  11. Oowaki, Y., Noguchi, M., Takagi, S., Takashima, D., Ono, M., Matsunaga, Y., Sunouchi, K., Kawaguchiya, H., Matsuda, S., Kamoshida, M., Fuse, T., Watanabe, S., Toriumi, A., Manabe, S., Hojo, A.: A Sub-0.1 m Circuit Design with Substrate-over-Biasing. In: Digest of Technical Papers of the Solid State Circuits Conference, pp. 88–89. IEEE INC (1998)

    Google Scholar 

  12. Miyazaki, M., Ono, G., Ishibashi, K.: A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltageCMOS with forward bias. IEEE Journal of Solid-State Circuits 37(2) (2002)

    Google Scholar 

  13. Tachibana, F., Sato, H., Yamashita, T., Hara, H., Kitahara, T., Nomura, S., Yamane, F., Tsuboi, Y., Seki, K., Matsumoto, S., Watanabe, Y., Hamada, M.: A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2 V design. In: CICC ’08: Proceedings of the 2008 IEEE Custom Integrated Circuits Conference, pp. 29–32 (2008)

    Google Scholar 

  14. Narendra, S., Keshavarzi, A., Bloechel, B., Borkar, S., De, V.: Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE Journal of Solid-State Circuits 38(5) (2003)

    Google Scholar 

  15. Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45nm design exploration. IEEE Transactions on Electron Devices 53(11), 2816–2823 (2006)

    Article  Google Scholar 

  16. Clark, L., Hoffman, E., Miller, J., Biyani, M., Liao, L., Strazdus, S., Morrow, M., Velarde, K., Yarch, M.: An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE Journal of Solid-State Circuits 36(11), 1599–1608 (2001)

    Article  Google Scholar 

  17. Ditzel, D.: Power Reduction using LongRun2 in Transmetas Efficeon Processor. In: Spring Processor Forum (2006)

    Google Scholar 

  18. Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V., Wilson, H., Vangal, S., Pangal, A., Seligman, E., Nair, R., Keshavarzi, A., Bloechel, B., Dermer, G., Mooney, R., Borkar, N., Borkar, S., De, V.: 1.1 v 1 ghz communications router with on-chip body bias in 150 nm cmos. In: ISSCC ’02: IEEE International Solid-State Circuits Conference Digest of Technical Papers, p. 270 (2002)

    Google Scholar 

  19. Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., De, V.: Parameter variations and impact on circuits and microarchitecture. In: Proceedings of the 40th conference on Design automation, pp. 338–342. ACM New York, NY, USA (2003)

    Google Scholar 

  20. Ono, G., Miyazaki, M.: Threshold-voltage balance for minimum supply operation [LV CMOS chips]. IEEE Journal of Solid-State Circuits 38 (2003)

    Google Scholar 

  21. Teodorescu, R., Nakano, J., Tiwari, A., Torrellas, J.: Mitigating parameter variation with dynamic fine-grain body biasing. In: MICRO 40: Proceedings of the 40th annual ACM/IEEE International Symposium on Microarchitecture (2007)

    Google Scholar 

  22. Ghosh, A., Rao, R., Kim, J., Chuang, C., Brown, R.: On-Chip Process Variation Detection using Slew-Rate Monitoring Circuit. In: Proceedings of the 21st International Conference on VLSI Design, pp. 143–149. IEEE Computer Society (2008)

    Google Scholar 

  23. Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.: Area-efficient linear regulator with ultra-fast load regulation. IEEE Journal of Solid-State Circuits 40(4) (2005)

    Google Scholar 

  24. Herbert, S., Marculescu, D.: Variation-aware dynamic voltage/frequency scaling. In: High-Performance Computer Architecture (2009)

    Google Scholar 

  25. Hardavellas, N., Somogyi, S., Wenisch, T., Wunderlich, R., Chen, S., Kim, J., Falsafi, B., Hoe, J., Nowatzyk, A.: Simflex: A fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. ACM SIGMETRICS Performance Evaluation Review 31(4), 34 (2004)

    Article  Google Scholar 

  26. Skadron, K., Stan, M.R., Huang, W., Velusamy, S., Sankaranarayanan, K., Tarjan, D.: Temperature-aware microarchitecture. In: ISCA ’03: Proceedings of the 30th annual international symposium on Computer architecture, pp. 2–13 (2003)

    Google Scholar 

  27. Kosakowski, M., Wittmann, R., Schardein, W., Jentschel, H.J.: Yield prediction and optimization to gain accurate devices for analog design in nonideal nanoscale processes. In: 10th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD ’08). Erfurt (2008)

    Google Scholar 

  28. Böker, F.: Multivariate Verfahren. Universität Göttingen, Institut für Statistik und Ökonometrie (2006)

    Google Scholar 

  29. Hinkley, D.V.: On the ratio of two correlated normal random variables. Imperial College, Biometrica (1969)

    Google Scholar 

  30. Mühlbach, G.: Repetitorium der Wahrscheinlichkeitsrechnung und Statistik. Binomi (2002)

    Google Scholar 

  31. Kosakowski, M., Wittmann, R., Schardein, W.: Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes. In: 21st Annual IEEE International SOC Conference. Newport Beach (2008)

    Google Scholar 

  32. Wittmann, R., Kakerow, R., Bothe, H., Schardein, W.: A multi-purpose digital controlled potentiometer IP-core for nano-scale integration. In: IP08. Grenoble (2008)

    Google Scholar 

  33. Shi, C., Wilson, J., Lsmail, M. Design techniques for improving intrinsic accuarcy of resistor string DHLS, IEEE international symposium on circuits and systems, 2009

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Alyssa C. Bonnoit .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Bonnoit, A.C., Wittmann, R. (2012). Consequences for Circuit Design and Case Studies. In: Dietrich, M., Haase, J. (eds) Process Variations and Probabilistic Integrated Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6621-6_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6621-6_5

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-6620-9

  • Online ISBN: 978-1-4419-6621-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics