Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics

Part of the Integrated Circuits and Systems book series (ICIR)


SRAM has been generally characterized with some SNM [12] from the voltage–voltage (VV) plots or the Icrit from the current–voltage (IV) plots. They do indicate the robustness of the SRAM operations but would not provide sufficient information for SRAM designers, as to the possible SRAM yield and the redundancy requirements. One way to estimate SRAM yield is based on the expected fail count with the Poisson distribution
$$ {\hbox{YIELD}} = \sum\limits_{n = 0}^k {\tfrac{{{\lambda^n}\exp ( - \lambda )}}{{n!}}} $$
where k is the maximum number of fails in the chip that can be repaired


Cell Node Metal Gate Perturbation Vector SRAM Cell Floating Body 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Lo S-H, Buchanan DA, Taur Y, Wang W (1997) Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Device Lett 18(5):209–211CrossRefGoogle Scholar
  2. 2.
    Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, Bost M, Brazier M, Buehler M, Cappellani A, Chau R, Choi C-H, Ding G, Fischer K, Ghani T, Grover R, Han W, Hanken D, Hattendorf M, He J, Hicks J, Heussner R, Ingerly D, Jain P, James R, Jong L, Joshi S, Kenyon C, Kuhn K, Lee K, Liu H, Maiz J, McIntyre B, Moon P, Neirynck J, Pae S, Parker C, Parsons D, Prasad C, Pipes L, Prince M, Ranade P, Reynolds T, Sandford J, Shifren L, Sebastian J, Seiple J, Simon D, Sivakumar S, Smith P, Thomas C, Troeger T, Vandervoorn P, Williams S, Zawadzki K (2007) A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. IEDM Tech Dig, 247–250Google Scholar
  3. 3.
    Kim YO, Manchanda L, Weber GR (1995) Oxynitride-dioxide composite gate dielectric process for MOS manufacture, US Patent Number 5,464,783, Nov. 7, 1995Google Scholar
  4. 4.
    Pae S, Agostinelli M, Brazier M, Chau R, Dewey G, Ghani T, Hattendorf M, Hicks J, Kavalieros J, Kuhn K, Kuhn M, Maiz J, Metz M, Mistry K, Prasad C, Ramey S, Roskowski A, Sandford J, Thomas C, Thomas J, Wiegand C, Wiedemer J (2008) BTI reliability of 45 nm high-K metal-gate process technology. Annual international reliability physics symposium proceedings, 2008, pp 352–357Google Scholar
  5. 5.
    Drapatz S, Georgakos G, Schmitt-Landsiedel D (2009) Impact of negative and positive bias temperature stress on 6 T-SRAM cells. Adv Radio Sci 7:191–196CrossRefGoogle Scholar
  6. 6.
    Feller W (1965) An introduction to probability theory and its applications. In: Random walk and ruin problems, Chapter 14. vol 1, 2nd edn, WileyGoogle Scholar
  7. 7.
    Wann C, Wong R, Frank D, Mann R, Ko S-B, Croce P, Lea D, Hoyniak D, Lee Y-M, Toomey J, Weybright M, Sudijono J (2005) SRAM cell design for stability methodology, 2005 IEEE VLSI-TSA international symposium on VLSI technology, pp 21–22Google Scholar
  8. 8.
    Rosa G.L., Loon NW, Rauch S, Wong R, Sudijono J (2006) Impact of NBTI induced statistical variation to SRAM cell stability. Annual international reliability physics symposium proceedings, 2006, pp 274–282Google Scholar
  9. 9.
    Wang L, Ye Q, Wong R, Liehr M (2007) Product burn-in stress impacts on SRAM array performance. International reliability physics symposium proceedings, 2007, pp 666–667Google Scholar
  10. 10.
    Yang S, Wong R, Hasumi R, Gao Y, Kim NS, Lee DH, Badrudduza S, Nair D, Ostermayr M, Kang H, Zhuang H, Li J, Kang L, Chen X, Thean A, Arnaud F, Zhuang L, Schiller C, Sun DP, The YW, Wallner J, Takasu Y, Stein K, Samavedam S, Jaeger D, Baiocco CV, Sherony M, Khare M, Lage C, Pape J, Sudijono J, Steegan AL, Stiffler S (2008), Scaling of 32 nm Low Power SRAM with High-K Metal Gate. IEEE International on Electron Devices Meeting, IEDM technical digest, 2008, pp 233–236Google Scholar
  11. 11.
    Bauer F, Georgakos G, Schmitt-Landsiedel D (2009) A design space comparison of 6T and 8T SRAM core-cells. Integrated circuit and system design. Power and timing modeling, optimization and simulation, Springer, pp 116–125Google Scholar
  12. 12.
    Seevinck E, List F, Lohstroh J (1987) Static noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circuits 22(5):748–754CrossRefGoogle Scholar
  13. 13.
    Schroder DK (2007) Negative bias temperature instability: what do we understand? Microelectron Reliab 47:841–852CrossRefGoogle Scholar
  14. 14.
    Wald A (1944) On cumulative sums of random variables. Ann Math Stat 15:283–296MathSciNetMATHCrossRefGoogle Scholar

Copyright information

© Springer US 2010

Authors and Affiliations

  1. 1.IBM Microelectronics DivisionHopewell JunctionUSA

Personalised recommendations