Let Sequence and Property Declarations Inference

Abstract

The beginning of wisdom is to call things by their right names.

Chinese proverb

In SystemVerilog, modules, programs, interfaces, checkers, functions, and tasks provide means for reuse, and for abstracting and hiding details. SystemVerilog assertions provide such means too. This is achieved using parameterized let , sequence , and property declarations. Their argument lists as well as instantiation semantics are quite different from the other reuse features. In addition, certain kinds of actual arguments can be inferred from the instantiation context. Similar to sequences and properties, let declarations allow to abstract expressions, making code more readable and reusable. They can be used anywhere, not only in assertions, but also one of their intended uses is for defining reusable parameterizable expressions for immediate and deferred assertions.