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Basic Properties

  • Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny
Chapter

Abstract

Properties play a central role in SVA because they form the bodies of concurrent assertions. A property is a temporal formula that can be either true or false on a given trace. An exception is disabled status of a property when the disable iff operator is used. See Sect. 13.1.1. As explained in Sect. 3.5.3, by trace we understand a series of all DUT signal values in time. Properties are interpreted over traces. In this chapter, we assume that each point on the trace corresponds to a tick of the clock on which the property is evaluated. This definition will not work for multiply clocked properties, but we currently limit our consideration to singly clocked properties only. The more general case is described in Chaps. 12, 13, and 20. Also, in formal verification (FV) we may assume that all the traces are infinite, which corresponds to the case when the property clock ticks infinitely many times. Of course, simulation traces are always finite. We informally describe the property semantics here, and defer the formal semantics of properties until Chap. 20.

Keywords

Property Operator Initial Procedure Strong Operator Formal Verification Boolean Expression 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 3.
    IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language (2005) IEEE Std 1800-2005, pp 1–648Google Scholar
  2. 9.
    Armoni R, Egorov S, Fraer R, Korchemny D, Vardi M (2005) Efficient LTL compilation for SAT-based model checking. In: ICCADGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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