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Assertion Statements

  • Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny
Chapter

Abstract

In this chapter, we describe SVA assertion statements: Assert statements Assume statements Restrict statements Cover statements

Keywords

Action Block Formal Verification Reactive Region Boolean Expression Device Under Test 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 2.
    IEEE Standard Verilog Hardware Description Language (2001) IEEE Std 1364-2001, pp 1–856Google Scholar
  2. 4.
    IEEE Standard for Verilog Hardware Description Language (2006) IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), pp 1–560Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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