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Future Enhancements

  • Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny
Chapter

Abstract

When the IEEE 1800–2009 SystemVerilog Standard was being completed, several issues and proposals in the assertions area remained unresolved due to time constraints and thus were not included. It is likely that a new version of the standard will be developed within a couple of years. Some of the unresolved proposals will make their way into that new version. Furthermore, as users and EDA community deploy the 2009 enhancements, requirements for new features will arise and will be addressed. To conclude our expose of the 2009 SystemVerilog Assertions, in this chapter we wish to mention at least some of the enhancements that we think should appear in any future standard without explicating details of syntax and semantics because it will likely emerge from the Standards committee in a different form. Most of the enhancements address the checker construct, and thus pertain to the creation of more effective checker libraries. As Niels Bohr stated, “prediction is difficult”, hence the contents of this chapter should be taken with a grain of salt.

Keywords

Free Variable Formal Argument Future Standard Argument Definition Conditional Assignment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Scince+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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