SystemVerilog Language and Simulation Semantics Overview

  • Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny


SystemVerilog language evolved from Verilog with three main goals: 1. To add features for describing test benches such that the stimulus generation portion of verification can go hand in hand with the design portion, replacing troublesome ad-hoc means for generating stimuli. Testbenches are often written using Verification Programming Interface(VPI) [7] to connect to external means such as verification languages, C/C + + programs [53], and scripts. 2. To add features for checking the expected behavior in simulation and formal methods. These features are related to assertions. 3. To simplify expressing hardware designs by providing language constructs such as struct typedef, and new variants of always procedure.


Time Slot Design Code Event Control Reactive Region Simulation Engine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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