An important mechanism for determining whether design validation sufficiently verified the design on hand is to collect “coverage” information, both structural and functional. This chapter describes how assertions can be used to gather functional coverage information using cover property and cover sequence statements. It is mainly suitable to collect information about the occurrences (or not) of some sequences of events. SystemVerilog provides another mechanism for collecting coverage, called covergroups. They are particularly suitable for gathering information about the occurrence of data patterns and their cross correlation. Often, it is important to detect a particular sequence of events and then initiate collecting coverage on data patterns. This can be achieved by combining assertion coverage with that of covergroups.