• Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny


An important mechanism for determining whether design validation sufficiently verified the design on hand is to collect “coverage” information, both structural and functional. This chapter describes how assertions can be used to gather functional coverage information using cover property and cover sequence statements. It is mainly suitable to collect information about the occurrences (or not) of some sequences of events. SystemVerilog provides another mechanism for collecting coverage, called covergroups. They are particularly suitable for gathering information about the occurrence of data patterns and their cross correlation. Often, it is important to detect a particular sequence of events and then initiate collecting coverage on data patterns. This can be achieved by combining assertion coverage with that of covergroups.


Cover Sequence Action Block Boolean Expression Functional Coverage Cover Property 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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    Spear C (2008) SystemVerilog for verification, a guide to learning the testbench language features. Springer, Norwell, MA, USAMATHGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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