• Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny


This chapter discusses the mechanics of declaring clocks and the rules that determine their scoping, including default clocking. Many concurrent assertions of practical interest are singly clocked, meaning that all parts of the assertion are governed by a single clocking event. Other concurrent assertions have portions that fall under the scopes of two or more clocking events and are called multiply clocked. SystemVerilog 2009 relaxes the rules on where the clocking event may change, allowing, e.g., clock changes after ##0 and |-> that were previously illegal.


Boolean Expression Actual Argument Event Expression Evaluation Attempt Clock Tick 
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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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