Aligning chips face-to-face for dense capacitive communication

  • John E. CunninghamEmail author
  • Ashok V. Krishnamoorthy
  • Ivan Shubin
  • James G. Mitchell
  • Xuezhe Zheng
Part of the Integrated Circuits and Systems book series (ICIR, volume 0)


Conductive electrical interconnections and on-chip transceivers have long been used to provide reliable interconnections between VLSI electronic components, and have dominated the interconnect hierarchy for reasons of manufacturing cost, system packaging, and ease-of-use. VLSI linewidths and on-chip clock speeds have continued to scale, putting pressures on the ability of traditional wires to achieve the offchip bandwidths necessary to fully and efficiently utilize the resources available onchip. When designing chip input and output circuits that communicate conductively, electronic circuit and system designers must design with the constraints of VLSI packages and circuit boards by using advanced circuit techniques such as predistortion, equalization, multilevel coding, and digitally controlled feed-forward clock and data recover blocks commonly referred to as serializer-deserializer (SerDes) transceivers. However, this generally increases the area and power consumption and limits the maximum number of I/O circuits per chip. Current best-in-class Serdes transceivers are expected to yield signaling densities between 1-5 terabits per second per square centimeter (Tbps/cm2) [1].


Silicon Chip Thermal Compression Scanning Electron Microscope Microphotograph Chip Separation Chip Bonding 
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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • John E. Cunningham
    • 1
    Email author
  • Ashok V. Krishnamoorthy
    • 1
  • Ivan Shubin
    • 1
  • James G. Mitchell
    • 2
  • Xuezhe Zheng
    • 1
  1. 1.Sun Microsystems Chief Technology OrganizationSan DiegoUSA
  2. 2.Sun Microsystems Chief Technology OrganizationMenlo ParkUSA

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