Aligning chips face-to-face for dense capacitive communication
- 761 Downloads
Conductive electrical interconnections and on-chip transceivers have long been used to provide reliable interconnections between VLSI electronic components, and have dominated the interconnect hierarchy for reasons of manufacturing cost, system packaging, and ease-of-use. VLSI linewidths and on-chip clock speeds have continued to scale, putting pressures on the ability of traditional wires to achieve the offchip bandwidths necessary to fully and efficiently utilize the resources available onchip. When designing chip input and output circuits that communicate conductively, electronic circuit and system designers must design with the constraints of VLSI packages and circuit boards by using advanced circuit techniques such as predistortion, equalization, multilevel coding, and digitally controlled feed-forward clock and data recover blocks commonly referred to as serializer-deserializer (SerDes) transceivers. However, this generally increases the area and power consumption and limits the maximum number of I/O circuits per chip. Current best-in-class Serdes transceivers are expected to yield signaling densities between 1-5 terabits per second per square centimeter (Tbps/cm2) .
KeywordsSilicon Chip Thermal Compression Scanning Electron Microscope Microphotograph Chip Separation Chip Bonding
Unable to display preview. Download preview PDF.
- 4.D. Hopkins, A. Chow, R. Bosnyak, B. Coates, J. Ebergen, S. Fairbanks, J. Gainsley, R. Ho, J. Lexau, F. Liu, T. Ono, J. Schauer, I. Sutherland, R. Drost, “Circuit techniques to enable 430 Gb/s/mm/mm proximity communication,” Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2007, pp. 368–369.CrossRefGoogle Scholar
- 5.W. Menz, J. Mohr, O. Paul, Microsystem technology, Wiley-VCH, CITY, 2000, p. 223.Google Scholar
- 6.I. Shubin, E.M. Chow, J. Cunningham, D. DeBruyker, C. Chua, B. Cheng, J. Knights, K. Sahasrabuddhe, Y. Luo, A. Chow, J. Simons, A.V. Krishnamoorthy, R. Hopkins, R. Drost, R. Ho, D. Douglas, J. Mitchell, “Novel Packaging with Rematable Spring Interconnect Chips for MCM,” 59th Electronic Components and Technology Conference, San Diego, 2009.Google Scholar
- 7.A.N. Cleland, Foundations of Nanomechanics, Ch. 10, 2003, Springer-Verlag, Berlin- Heildelberg.Google Scholar
- 8.J.E. Cunningham, X. Zheng, I. Shubin, R. Ho, J. Lexau, A.V. Krishnamoorthy, M. Asghari, D. Feng, J. Luff, H. Liang and C.-C. Kung, “Optical Proximity Communication in Packaged SiPhotonics,” Proceedings of the 5th IEEE International Conference on Group IV Photonics, FB8, 2008, pp. 383–385.Google Scholar
- 10.A.V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li; I. Shubin, J.E. Cunningham, “The integration of silicon photonics and VLSI electronics for computing systems intra-connect”, Proceedings, SPIE Photonics West, Vol. 7220: Silicon Photonics IV, 2009, pp. 1–12.Google Scholar