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Power delivery, signaling and cooling for 2D and 3D integrated systems

  • Muhannad Bakir
  • Gang Huang
  • Bing Dang
Chapter
Part of the Integrated Circuits and Systems book series (ICIR, volume 0)

Abstract

As gigascale integrated (GSI) technology progresses beyond the 45 nm generation, the performance of a monolithic system-on-a-chip (SoC) has failed by progressively greater margins to reach the “intrinsic limits” of each particular generation of technology [1]. The root cause of this lag is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high-performance SoC. The most serious obstacle that blocks fulfillment of the ultimate performance of an SoC is inferior heat removal.

Keywords

Solder Bump Very Large Scale Integration Power Delivery Thermal Interface Material Microchannel Heat Sink 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    M.S. Bakir, J.D. Meindl. Integrated interconnect technologies for 3D nanoelectronic systems. Artech House, Boston, 2009.Google Scholar
  2. 2.
    Semiconductor Industry Association, “International Technology Roadmap for Semiconductors (ITRS),” 2007.Google Scholar
  3. 3.
    R. Prasher, “Thermal interface materials: historical perspective, status, and future directions,” Proceedings of the IEEE, vol. 94, 2006, pp. 1571–1586.CrossRefGoogle Scholar
  4. 4.
    G. Schrom, P. Hazucha, H. Jae-Hong, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De, “Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90 nm technology generation,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design, 2004, pp. 263–268.Google Scholar
  5. 5.
    D. Mallik, K. Radhakrishnan, J. He, C.-P. Chiu, T. Kamgaing, D. Searls, and J.D. Jackson, “Advanced package technologies for high performance systems,” Intel Technology Journal, vol. 9, 2005, pp. 259–271.CrossRefGoogle Scholar
  6. 6.
    P. Hazucha, G. Schrom, H. Jaehong, B.A. Bloechel, P. Hack, G.E. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar, “A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package,” IEEE Journal of Solid-State Circuits, vol. 40, 2005, pp. 838–845.CrossRefGoogle Scholar
  7. 7.
    K. Shakeri and J.D. Meindl, “Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI),” IEEE Transactions on Electron Devices, vol. 52, 2005, pp. 1087–1096.CrossRefGoogle Scholar
  8. 8.
    D.A.B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proceedings of the IEEE, vol. 88, 2000, pp. 728–749.CrossRefGoogle Scholar
  9. 9.
    D. Huang, T. Sze, A. Landin, R. Lytel, and H.L. Davidson, “Optical interconnects: out of the box forever?” IEEE Journal of Selected Topics in Quantum Electronics, vol. 9, 2003, pp. 614–623.CrossRefGoogle Scholar
  10. 10.
    M. Lipson, “Overcoming the limitations of microelectronics using Si nanophotonics: solving the coupling, modulation and switching challenges,” Journal of Nanotechnology, vol. 15, 2004, pp. 622–627.CrossRefGoogle Scholar
  11. 11.
    A.G. Kirk, D.V. Plant, M.H. Ayliffe, M. Chateauneuf, and F. Lacroix, “Design rules for highly parallel free-Space optical interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 9, 2003, pp. 531–547.CrossRefGoogle Scholar
  12. 12.
    C. Debaes, M. Vervaeke, V. Baukens, H. Ottevaere, P. Vynck, P. Tuteleers, B. Volckaerts, W. Meeus, M. Brunfaut, J. Van Campenhout, A. Hermanne, and H. Thienpont, “Low-cost microoptical modules for MCM level optical interconnections,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 9, 2003, pp. 518–530.CrossRefGoogle Scholar
  13. 13.
    Y. Ishii, S. Koike, Y. Arai, and Y. Ando, “SMT-compatible large-tolerance ‘OptoBump’ interface for interchip optical interconnections,” IEEE Transactions on Advanced Packaging, vol. 26, 2003, pp. 122–127.CrossRefGoogle Scholar
  14. 14.
    X. Wang, F. Kiamilev, P. Gui, J. Ekman, G.C. Papen, M.J. McFadden, M.W. Haney, and C. Kuznia, “A 2-Gb/s optical transceiver with accelerated bit-error-ratio test capability,” Journal of Lightwave Technology, vol. 22, 2004, pp. 2158–2167.CrossRefGoogle Scholar
  15. 15.
    J.W. Joyner, P. Zarkesh-Ha, and J.D. Meindl, “Global interconnect design in a three-dimensional system-on-a-chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, 2004, pp. 367–372.CrossRefGoogle Scholar
  16. 16.
    G.G. Shahidi, “Evolution of CMOS technology at 32 nm and beyond,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2007, pp. 413–416.Google Scholar
  17. 17.
    G. Huang, M. Bakir, A. Naeemi, H. Chen, and J.D. Meindl, “Power delivery for 3D chip stacks: physical modeling and design implication,” emphProceedings of the IEEE Conference on the Electrical Performance of Electronic Packaging, 2007, pp. 205–208.Google Scholar
  18. 18.
    H. Ishikuro, N. Miura, and T. Kuroda, “Wideband inductive-coupling interface for high-performance portable system,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2007, pp. 13–20.Google Scholar
  19. 19.
    J.Q. Lu, Y. Kwon, G. Rajagopalan, M. Gupta, J. McMahon, K.W. Lee, R.P. Kraft, J.F. McDonald, T.S. Cale, R.J. Gutmann, B. Xu, E. Eisenbraun, J. Castracane, and A. Kaloyeros, “A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects,” Proceedings of the IEEE International Interconnect Technology Conference, 2002, pp. 78–80.Google Scholar
  20. 20.
    C.S. Tan, K.N. Chen, A. Fan, and R. Reif, “A back-to-face silicon layer stacking for three-dimensional integration,” Proceedings of the IEEE International SOI Conference, 2005, pp. 87–89.CrossRefGoogle Scholar
  21. 21.
    J.A. Burns, B.F. Aull, C.K. Chen, C.-L. Chen, C.L. Keast, J.M. Knecht, V. Suntharalingam, K. Warner, P.W. Wyatt, and D.R.W. Yost, “A wafer-scale 3D circuit integration technology,” IEEE Transactions on Electron Devices, vol. 53, 2006, pp. 2507–2516.CrossRefGoogle Scholar
  22. 22.
    D.J. Witte, F. Crnogorac, D.S. Pickard, A. Mehta, Z. Liu, B. Rajendran, P. Pianetta, and R.F.W. Pease, “Lamellar crystallization of silicon for 3-dimensional integration,” Microelectronic Engineering, vol. 84, 2007, pp. 118.CrossRefGoogle Scholar
  23. 23.
    J. Feng, Y. Liu, P.B. Griffin, and J.D. Plummer, “Integration of Germanium-on-Insulator and Silicon MOSFETs on a silicon substrate,” IEEE Electron Device Letters, vol. 27, 2006, pp. 911–913.CrossRefGoogle Scholar
  24. 24.
    M.S. Bakir, B. Dang, and J.D. Meindl, “Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2007, pp. 421–428.Google Scholar
  25. 25.
    M.S. Bakir and J.D. Meindl, “Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration,” IEEE Transactions on Electron Devices, vol. 51, 2004, pp. 1069–1077.CrossRefGoogle Scholar
  26. 26.
    M.S. Bakir, T.K. Gaylord, K.P. Martin, and J.D. Meindl, “Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections,” IEEE Photonics Technology Letters, vol. 15, 2003, pp. 1567–1569.CrossRefGoogle Scholar
  27. 27.
    O.O. Ogunsola, H.D. Thacker, B.L. Bachim, M.S. Bakir, J. Pikarsky, T.K. Gaylord, and J.D. Meindl, “Chip-level waveguide-mirror-pillar optical interconnect structure,” IEEE Photonics Technology Letters, vol. 18, 2006, pp. 1672–1674.CrossRefGoogle Scholar
  28. 28.
    B. Dang, M.S. Bakir, and J.D. Meindl, “Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink,” IEEE Electron Device Letters, vol. 27, 2006, pp. 117–119.CrossRefGoogle Scholar
  29. 29.
    B. Dang, “Integrated input/output interconnection and packaging for GSI,” Ph.D. Thesis, Georgia Institute of Technology, 2006.Google Scholar
  30. 30.
    B. Dang, P. Joseph, M.S. Bakir, T. Spencer, P. Kohl, and J.D. Meindl, “Wafer-level microfluidic cooling interconnects for GSI,” Proceedings of the IEEE International Interconnect Technology Conference, 2005, pp. 180–182.CrossRefGoogle Scholar
  31. 31.
    M.S. Bakir, B. Dang, O. Ogunsola, and J.D. Meindl, “‘Trimodal’ wafer-level package: fully compatible electrical, optical, and fluidic chip I/O interconnects,” Proceedings of the Electronic Component and Technology Conference, 2007.Google Scholar
  32. 32.
    M.S. Bakir, D. Bing, O.O.A. Ogunsola, R. Sarvari, and J.D. Meindl, “Electrical and optical chip i/o interconnections for gigascale systems,” IEEE Transactions on Electron Devices, vol. 54, 2007, pp. 2426–2437.CrossRefGoogle Scholar
  33. 33.
    M.S. Bakir, A.L. Glebov, M.G. Lee, P.A. Kohl, and J.D. Meindl, “Mechanically flexible chip- to-substrate optical interconnections using optical pillars,” IEEE Transactions on Advanced Packaging, vol. 31, 2008, pp. 143–153.CrossRefGoogle Scholar
  34. 34.
    A.L. Glebov, D. Bhusari, P. Kohl, M.S. Bakir, J.D. Meindl, and M.G. Lee, “Flexible pillars for displacement compensation in optical chip assembly,” IEEE Photonics Technology Letters, vol. 18, 2006, pp. 974–976.CrossRefGoogle Scholar
  35. 35.
    H.Y. Zhang, D. Pinjala, T.N. Wong, and Y.K. Joshi, “Development of liquid cooling techniques for flip chip ball grid array packages with high heat flux dissipations,” IEEE Transactions on Components and Packaging Technology, vol. 28, 2005, pp. 127–135.MATHCrossRefGoogle Scholar
  36. 36.
    E.G. Colgan, B. Furman, A. Gaynes, W. Graham, N. LaBianca, J.H. Magerlein, R.J. Polastre, M.B. Rothwell, R.J. Bezama, R. Choudhary, K. Marston, H. Toy, J. Wakil, and J. Zitz, “A practical implementation of silicon microchannel coolers for high power chips,” Proceedings of the IEEE Semiconductor Thermal Measurement and Management Symposium, 2005, pp. 1–7.Google Scholar
  37. 37.
    D.B. Tuckerman and R.F.W. Pease, “High-performance heat sinking for VLSI,” IEEE Electron Device Letters, vol. 2, 1981, pp. 126–129.CrossRefGoogle Scholar
  38. 38.
    C.K. King, D. Sekar, M.S. Bakir, B. Dang, J. Pikarsky, and J.D. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” Proceedings of the Electronics Components and Technology Conference, 2008.Google Scholar
  39. 39.
    D. Sekar, C. King, B. Dang, T. Spencer, H.D. Thacker, P. Joseph, M.S. Bakir, and J.D. Meindl, “A 3D-IC technology with integrated microchannel cooling,” Proceedings of the International Interconnect Technology Conference, 2008.Google Scholar
  40. 40.
    M.S. Bakir, C. King, D. Sekar, H.D. Thacker, B. Dang, G. Huang, A. Naeemi, and J.D. Meindl, “3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2008.Google Scholar
  41. 41.
    H.D. Thacker, O. Ogunsola, A. Carson, M.S. Bakir, and J.D. Meindl, “Optical through-wafer interconnects for 3D hyper-integration,” Proceedings of the IEEE Lasers and Electro-Optics Society Annual Meeting, 2006, pp. 28–29.Google Scholar
  42. 42.
    J.H. Wu, J. Scholvin, and J.A. del Alamo, “A through-wafer interconnect in silicon for RFICs,” IEEE Transactions on Electron Devices, vol. 51, 2004, pp. 1765–1771.CrossRefGoogle Scholar
  43. 43.
    J.D. Meindl, “Low Power Microelectronics: Retrospect and Prospects,” Proceedings of IEEE, vol. 83, 1995, pp. 619–635.CrossRefGoogle Scholar
  44. 44.
    M. Swaminathan and E. Engin. Power Integrity: Modeling and Design for Semiconductor and Systems. Prentice Hall PTR, 2007.Google Scholar
  45. 45.
    H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions,” IEEE Design and Test of Computers, vol. 20, no. 3, 2003, pp. 23–31.Google Scholar
  46. 46.
    K.L. Wong, T. Rahal-Arabi, M. Ma, and G. Taylor, “Enhancing Microprocessor Immunity to Power Supply Noise with Clock-Data Compensation,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, 2006.CrossRefGoogle Scholar
  47. 47.
    W.D. Becker, J. Eckhardt, R.W. Frech, G.A. Katopis, E. Klink, M.F. McAllister, T.G. MacNamara, P. Muench, S.R. Richter, and H.H. Smith, “Modeling, Simulation, and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systems,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, part B, vol. 21, 1998, pp. 157–163.CrossRefGoogle Scholar
  48. 48.
    A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, “Design and Analysis of Power Distribution Networks in PowerPC Microprocessors,” Design Automation Conference, 1998, pp. 738–743.Google Scholar
  49. 49.
    R. Tummala. Fundamentals of Microsystems Packaging. McGraw Hill, 2001.Google Scholar
  50. 50.
    G. Huang, D. Sekar, A. Naeemi, K. Shakeri, and J.D. Meindl, “Compact physical models for power supply noise and chip/package co-design of gigascale integration”, Proceedings of the Electronic Component and Technology Conference 2007.Google Scholar
  51. 51.
    M.S. Bakir, H. A. Reed, H.D. Thacker, P.A. Kohl, K.P. Martin, and J.D. Meindl, “Sea of Leads (SoL) ultrahigh density wafer level chip input/output interconnections,” IEEE Transactions on Electron Devices, vol. 50, no. 10, 2003, pp. 2039–2048.CrossRefGoogle Scholar
  52. 52.
    Semiconductor Industry Association, “International Technology Roadmap for Semiconductors (ITRS),” 2004.Google Scholar
  53. 53.
    K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, “3D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proceedings of the IEEE, vol. 89, no. 5, 2001, pp. 602–633.CrossRefGoogle Scholar
  54. 54.
    J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C.S. Patel, R. Polastre, K. Sakuma, E. Sprogis, C.K. Tsang, and S.L. Wright, “3D chip stacks and silicon packaging technology using through-silicon-vias (TSV) for systems integration,” 3D System Integration Conference (3D-SIC), 2007.Google Scholar
  55. 55.
    J. Held, J. Bautista, and S. Koehl, “From a few cores to many: a tera-scale computing research overview,” Research at Intel White Paper.Google Scholar
  56. 56.
    G. Huang, M. Bakir, A. Naeemi, H. Chen, and J.D. Meindl, “Power delivery for 3D chip stacks: physical modeling and design implication,” Proceedings of the Electrical Performance of Electronic Packaging, 2007, pp. 205–208.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Georgia Institute of TechnologyAtlantaUSA
  2. 2.Intel Corporation, Ultra Mobility GroupAustinUSA
  3. 3.IBM T. J. Watson Research CenterYorktown HeightsUSA

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