Abstract
The past quarter-century has seen an explosive growth in the performance of computer systems. One of the first widely popular personal computers was a mid-1980s IBM PC, running on a 4.77 MHz Intel 8088 processor, stuffed with 256 KB of system memory (plus another 384 KB on an expansion card), displaying 640x200 black-and-white graphics, and storing data on 360 KB 5.25-inch floppy disks. In 2009, a typical workstation configuration sold by Sun Microsystems, the Ultra 24 Workstation, used a 3 GHz Intel Quad Core 2 processor with 8 GB of memory, displayed 2560x1600 graphics on a 30-inch LCD monitor using an Nvidia Quadro NVS 290 accelerator card, with up to 1.8 TB of Serial-Attached SCSI drives spinning at 15 krpm.
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References
G. Moore, “Cramming more components onto integrated circuits,” Electronics Magazine, vol. 38, no. 8, 1965.
M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, K. Bernstein, “Scaling, power, and the future of CMOS,” IEEE International Electron Devices Meeting, 2005, pp. 7–15.
J. Hennessey, D. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, Morgan-Kaufmann, 2002.
S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, J. Chang, R. Varada, M. Ratta, S. Kottapalli, “A 45nm 8-Core Enterprise Xeon(R) Processor,” IEEE International Solid State Circuits Conference, 2009.
R. Ho, T. Ono, F. Liu, R. Hopkins, A. Chow, J. Schauer, R. Drost, “High-speed and low-energy capacitively driven wires,” IEEE Journal of Solid State Circuits, Vol. 43, No. 1, January 2008.
E. Mensink, D. Schinkel, E. Klumperink, E. van Tuijl, B. Nauta, “A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects”, IEEE International Solid State Circuits Conference, 2007.
B. Kim, V. Stojanovic, “A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS,” IEEE International Solid State Circuits Conference, 2009.
G. Moore, “No exponential is forever: but ‘Forever’ can be delayed!” IEEE International Solid State Circuits Conference, 2003.
J. Seo, R. Ho, J. Lexau, M. Dayringer, D. Sylvester, D. Blaauw, “High bandwidth and low energy on-chip signaling using adaptive pre-emphasis in 90nm CMOS,” IEEE International Solid State Circuits Conference, 2010.
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Ho, R., Drost, R. (2010). Introduction to Coupled Data Technologies. In: Ho, R., Drost, R. (eds) Coupled Data Communication Techniques for High-Performance and Low-Power Computing. Integrated Circuits and Systems, vol 0. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6588-2_1
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