ESD Design for Signal Path Analog

Chapter

Abstract

The purpose of this and the following chapters is to demonstrate the implementation of different ESD protection approaches specific to analog products. Two major categories of analog products are used as examples demonstrating ESD protection challenges and solutions: the signal path and the power management products. The first category is addressed in this chapter. Chapter 7 is focused on the specifics of power management products. These products include low-voltage and high-voltage integrated DC–DC converters and controllers, LED and display drivers, and other power products.

Keywords

Migration 

References

  1. [117]
    Stadler W, Brodbeck T, Gartner R, Gossner H (2006) Cable discharges into communication interfaces. Proc. EOS/ESD Symposium, 144–151.Google Scholar
  2. [120]
    Deatherage J, Jones D (2000) Multiple factors trigger cable discharge events in Ethernet LANs. Electron Design 48(25):111–116.Google Scholar
  3. [119]
    Pischl N (2005) ESD transfer through Ethernet magnetics. Proc. Intl. EMC Symposium, 356–363.Google Scholar
  4. [118]
    Pommerenke D (2001) Charged cable event. IEEE 802.3 Cable Discharge Ad-Hoc, February 2001.Google Scholar
  5. [114]
    Monticelli D (2004) The future of complementary bipolar. BCTM, 21–25.Google Scholar
  6. [105]
    Concannon A (2007–2008) National Semiconductor, Internal Engineering Analysis Report.Google Scholar
  7. [116]
    Jansen P, Thijs S. Linten D, et al. (2005) RF ESD protection strategies – the design and performance trade-off challenges. Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 21–21 September 2005, 489–496.Google Scholar
  8. [115]
    Denison M, Murtaza S, Steinhoff R (2007) 25 V ESD NPN transistor optimized by distributed emitter ballasting using emitter contact area segmentation. Proc. Int. Rel. Phys. Symp., 604–605.Google Scholar
  9. [106]
    Anderson WR (2009) I/O Design Concepts for the ESD Engineer, International ESD Workshop, South Lake, Tahoe, 2009 Seminar #1.Google Scholar
  10. [121]
    Ram C (2007) Cable Discharge Event(CDE) Stress Simulation Test Procedure for Integrated Circuits. Texas Instruments.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.National SemiconductorSanta ClaraUSA
  2. 2.Angstrom Design AutomationSan JoseUSA

Personalised recommendations