Standard and ESD Devices in Integrated Process Technologies

  • Vladislav A. Vashchenko
  • Andrei Shibkov


In Chapter 2, conductivity modulation mechanisms were discussed based upon examples of these mechanisms in corresponding elementary semiconductor structures. The purpose of Chapter 3 is to describe how these conductivity modulation phenomena are realized in both standard devices supported by electrical design rules of given integrated process technology and free ESD devices developed in the process.

The pulsed safe-operating area (SOA) and physical limitations of the operation regime are discussed first for standard devices in typical integrated process technologies. Then, “free” ESD devices are described in greater detail specific to the device type.

The definition of a “free ESD device” assumes no additional process steps in device formation. A free ESD device can be built using only the available mask layers within physical limits of the process. The device can be formed using a self-aligned approach, where variation of the masks will not change the characteristics, or as a non-self-aligned device. In the last case, the device is sensitive to misalignment of the mask layers, which requires the use of additional measures to guarantee repeatable device characteristics (or acceptable parametric yields) within the specified parameter range.


Breakdown Voltage Gate Oxide Conductivity Modulation Avalanche Diode NMOS Device 
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  1. [48]
    Chung Y, Xu H, Ida R, Baird R (2006) Snapback breakdown dynamics and ESD susceptibility of LDMOS. Proc. Int. Rel. Phys. Symp., 352–355; Steinhoff R, Huang J-B, Hower P, Brodsky J (2003) Current filament movement and silicon melting in an ESD-robust DENMOS transistor. Proceed. EOS/ESD Symp., 220–268.Google Scholar
  2. [56]
    Renaud P, Gendron A, Bafleur M, Nolhier N (2007) High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology. Proceed. BCTM, 226–229.Google Scholar
  3. [40]
    LaFonteese D, Vashchenko VA, Korablev KG (2009) Breakdown voltage walkout effect in ESD protection devices. IRPS.Google Scholar
  4. [51]
    Chatterjee A, Polgreen T (1991) A low voltage triggering SCR for on-chip ESD protection at output and input pads. IEEE Electron Device Lett 12(1):21–22.CrossRefGoogle Scholar
  5. [41]
    Wu J, Rosenbaum E (2004) Gate oxide reliability under ESD-like pulse stress. IEEE Trans Educ 51(7):1192–1195.CrossRefGoogle Scholar
  6. [15]
    Vashchenko VA, Sinkevitch VF (1996) Current instability and burnout of HEMT structures. Solid-State Electron 39:851–856.CrossRefGoogle Scholar
  7. [9]
    Vashchenko VA, Sinkevitch VF (2008) Physical Limitations of Semiconductor Devices. Springer, Berlin.CrossRefGoogle Scholar
  8. [59]
    Concannon A (2005) National Semiconductor, Internal Engineering Analysis Report.Google Scholar
  9. [14]
    Sze S (1981) Physics of Semiconductor Devices. Wiley, New York, NY.Google Scholar
  10. [52]
    Chen JZ, Amerasekera A, Vrotos T (1995) Bipolar SCR ESD protection for high speed submicron bipolar/BiCMOS circuit frequency integrated circuits. IEDM, 337–340.Google Scholar
  11. [33]
    Scholz M, et al. (2008) On-wafer human metal model – system-level ESD stress on component level. Proc. RCJ EOS/ESD/EMC Symposium, 91–97.Google Scholar
  12. [55]
    Gendron A, Renaud P, Besse P, Salamero C, Bafleur M, Nolhier N (2006) Area-efficient reduced and no-snapback PNP-based ESD protection in advanced smart power technology. Proc. EOS/ESD Symposium, September 2006, 69–76.Google Scholar
  13. [50]
    Vashchenko VA, Concannon A, ter Beek A, Hopper P (2002) Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway. Proc. EOSESD Symposium, 101–110.Google Scholar
  14. [46]
    Charitat G (2001) Voltage handling capability and termination techniques of silicon power semiconductor devices. IEEE BCTM 10.5, 175–183.Google Scholar
  15. [45]
    Tasca D (1970) Pulsed power failure modes in semiconductors. IEEE Trans Nucl Sci NS-17:364–372.Google Scholar
  16. [57]
    Vashchenko VA, LaFonteese D (2009) System level and hot plug-in protection of high voltage transient pins. EOS/ESD Symposium.Google Scholar
  17. [7]
    Vashchenko VA, Hopper P (2005) Bipolar SCR ESD devices. Microelectron Reliab 45:457–471.CrossRefGoogle Scholar
  18. [49]
    Vashchenko VA, Lafonteese D (2009) System level and hot plug-in protection of high voltage transient pins. Proc. EOS/ESD Symposium.Google Scholar
  19. [44]
    Dwyer V, Franklin A, Campbell D (1991) Thermal failure in semiconductor devices. Solid-State Electron 33:553–560.CrossRefGoogle Scholar
  20. [58]
    Voldman S, Giessier S, Nakoe J, et al. (1998) Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks. Proc. EOS/ESD Symp., 151–160.Google Scholar
  21. [32]
    Hanwa. HBM, MMWaveform Capture System.Google Scholar
  22. [36]
    Vashchenko VA, Kuznetsov V, Hopper P (2007) Implementation of dual-direction SCR devices in analog CMOS process. Proc. EOSESD Symp., 75–79.Google Scholar
  23. [30]
    Keppens B, Mergens M, Armer J, et al. (2003) Active-area-segmentation (AAS) technique for compact ESD robust, fully silicided NMOS design. Proc. EOS/ESD Symp., 250–258.Google Scholar
  24. [54]
    Li J, Gauthier R, Chatty K, Kontos D, et al. (2005) PMOSFET-based ESD protection in 65 nm bulk CMOS technology for improved external latch-up robustness. Proc. EOS/ESD Symposium.Google Scholar
  25. [53]
    Vashchenko VA, LaFonteese D (2008) Lateral PNP BJT ESD protection devices. BCTM, 53–56.Google Scholar
  26. [34]
    Scholz M, et al. (2007) Calibrated wafer-level HBM measurements for quasi-static and transient device analysis. Proceedings of EOS/ESD Symposium, 89–94.Google Scholar
  27. [42]
    Vashchenko VA, Kindt W, Hopper P, ter Beek M (2004) Implementation of 60 V tolerant dual direction ESD protection in 5 V BiCMOS process for automotive application. Proc. EOS/ESD Symposium.Google Scholar
  28. [43]
    Wunsch D, Bell R (1968) Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages. IEEE Trans Nucl Sci NS-15:244–259.CrossRefGoogle Scholar
  29. [39]
    Wolf S (1990) Silicon Processing for VLSI Era, Vol. 2, Process Integration. Lattice Press, Sunset Beach, CA.Google Scholar
  30. [47]
    Vashchenko VA, ter Beek M (2005) ESD protection window targeting using LDMOS-SCR devices with Pwell-Nwell super-junction. Proc. IRPS, April 2005, 612–613.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.National SemiconductorSanta ClaraUSA
  2. 2.Angstrom Design AutomationSan JoseUSA

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