Verifying Peak Power Optimizations Using SPIN Model Checker

Abstract

Chapter 8 presents an algorithm for peak power reduction of designs generated using CAOS. The proposed algorithm exploits the fact that for a CAOS-based design, disabling appropriate actions in a clock cycle for reducing its peak power should not alter the functional behavior of the design. This is because for well-written CAOS designs, re-scheduling of the actions of a design for reducing its peak power will enable appropriate set of actions for execution (in future clock cycles) based on various fairness constraints, thus maintaining the overall behavior of the design. However, re-scheduling of the actions can result in changing the behavior of those CAOS designs which do not model the fairness constraints (related to the execution of the actions of a design) appropriately. Such designs may fail to produce a correct output when re-scheduling of their actions occurs. This stresses the need for verification of a CAOS-based design in order to ensure that its behavior is maintained after re-scheduling of its actions as done by the peak power reduction algorithm described in Chapter 8. Note that such re-scheduling of the actions of a design can also be done for other reasons such as constraints on the number of resources available.