Abstract
Dynamic power is an important component of the power consumption of a hardware design. In this chapter, we present two algorithms that target the reduction of dynamic power during the CAOS-based synthesis process and produce RTL that can be synthesized into power-efficient hardware. We also present experimental results to show that when a CAOS specification is compiled using these algorithms, the resulting hardware (without any additional gate-level power optimizations) has power/area/latency numbers comparable to those obtained by using the well-known industrial-strength power optimization RTL to gate-level synthesis tools such as Magma Blast Power or Synopsys Power Compiler.
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© 2010 Springer Science+Business Media, LLC
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Singh, G., Shukla, S.K. (2010). Dynamic Power Optimizations. In: Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6481-6_7
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DOI: https://doi.org/10.1007/978-1-4419-6481-6_7
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-6480-9
Online ISBN: 978-1-4419-6481-6
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