Dynamic Power Optimizations



Dynamic power is an important component of the power consumption of a hardware design. In this chapter, we present two algorithms that target the reduction of dynamic power during the CAOS-based synthesis process and produce RTL that can be synthesized into power-efficient hardware. We also present experimental results to show that when a CAOS specification is compiled using these algorithms, the resulting hardware (without any additional gate-level power optimizations) has power/area/latency numbers comparable to those obtained by using the well-known industrial-strength power optimization RTL to gate-level synthesis tools such as Magma Blast Power or Synopsys Power Compiler.


Clock Cycle Power Optimization Power Saving Advance Encryption Standard Switching Activity 
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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Intel CorporationAustinUSA
  2. 2.Bradley Department of Electrical & Computer EngineeringVirginia TechBlacksburgUSA

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