Advertisement

Scalable Folding and Interpolating ADC Design

  • Armin Tajalli
  • Yusuf Leblebici
Chapter

Abstract

Analog-to-digital converters (ADCs) are one of the most critical building blocks in mixed-signal integrated circuits. The signals in analog domain are generally required to be converted to digital signals with enough resolution for further processing in the digital part of a system. For this purpose, after amplifcation and fltering, input signal will be digitized by an ADC block. As the dynamic range and speed of operation in this block are both very critical, generally this part of circuit consumes a considerable amount of power. Therefore, design of ultra-low power ADC circuits is very demanding.

Keywords

Power Consumption Cyclical Code Gray Code Differential Pair Digital Part 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultra-low power ADC for distributed sensor networks,” in Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 255–258, Sep. 2002Google Scholar
  2. 2.
    J. Sauerbrey, D. Schmitt-Landseidel, and R. Thewes, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1251–1265, Jul. 2003Google Scholar
  3. 3.
    G. Bonfini, and et al., “An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications,” in IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51, no. 1, pp. 174–178, Jan. 2004Google Scholar
  4. 4.
    N. Verma and A. P. Chandrakasan, “An ultra low energy 12-b rate-resolution scalable SAR ADC for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007Google Scholar
  5. 5.
    H. -C. Hong and G.-M. Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161–2168, Oct. 2007Google Scholar
  6. 6.
    S. Gambini and J. Rabaey, “Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2348–2356, Nov. 2007CrossRefGoogle Scholar
  7. 7.
    M. van Elzakker, and et al., “A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), pp. 244–245, Feb. 2008Google Scholar
  8. 8.
    D. C. Daly and A. P. Chandrakasan, “A 6b 0.2-to0.9V highly digital flash ADC with comparator redundancy,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), pp. 554–555, Feb. 2008Google Scholar
  9. 9.
    J. van Valburg and R. J. van de Plassche, “An 8-b 650-MHz folding ADC,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1662–1666, Dec. 1992Google Scholar
  10. 10.
    R. Y. van de Plassche and P. Baltus, “An 8-bit 100-MHz full-Nyquist analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1334–1344, Dec. 1988Google Scholar
  11. 11.
    S. Limotyrakis, K.-Y. Nam, and B. A. Wooley, “Analysis and simulation of distortion in folding and interpolating A/D converters,” in IEEE Transactions on Circuits and Systems-II: Analog and Digital Processings, vol. 49, no. 3, pp. 161–169, Mar. 2002Google Scholar
  12. 12.
    P. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, Jun. 2005Google Scholar
  13. 13.
    M. P. Flynn and D. J. Allstot, “CMOS folding A/D converters with current-mode interpolation,” IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1248–1257, Sep. 1996Google Scholar
  14. 14.
    M. Babaie, H. Movahedian, M. Sharif Bakhtiar, “A novel method for systematic error prediction of CMOS folding and interpolating ADC,” in Asia-Pacific Circuits and Systems Conference (APCCAS), pp. 1768–1771, 2006Google Scholar
  15. 15.
    A. Tajalli, Y. Leblebici, and E. J. Brauer, “Implementing ultra-high-value floating tunable CMOS resistor,” in IET Electronics Letters, vol. 44, no. 5, pp. 349–350, Feb. 2008Google Scholar
  16. 16.
    A. Tajalli, E. J. Brauer, E. Vittoz, and Y. Leblebici, “Subthreshold source-coupled logic circuits for ultra-low-power applications,” IEEE J. Solid-State Circuits, vol. 43, pp. 1699–1710, Jul. 2008Google Scholar
  17. 17.
    M. Beikahmadi, A. Tajalli, and Y. Leblebici, “A subthreshold SCL based pipelined encoder for ultra-low power 8-bit folding/interpolating ADC,” in Proceedings of The Nordic Microelectronics Event (NORCHIP), pp. 9–12, Tallin, Estonia, Nov. 2008Google Scholar
  18. 18.
    R. Roovers and M. S. J. Steyaert, “1 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 31, pp. 938–944, Jul. 1996Google Scholar
  19. 19.
    Y. Li, “Design of high speed folding and interpolating analog-to-digital converter,” Ph.D. Diss., Texas A&M Univ., May 2003Google Scholar
  20. 20.
    A. G. W. Venes and R. J. van de Plassche, “An 80-MHz, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. 1846–1853, Dec. 1996Google Scholar
  21. 21.
    B. Nauta and A. G. W. Venes, “A 70-MS/s 100-mW 8-b CMOS folding and interpolating A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 1302–1308, Dec. 1995Google Scholar
  22. 22.
    A. Tajalli and Y. Leblebici “Nanowatt range folding-interpolating ADC using subthreshold source-coupled circuits,” J. Low-Power Electron., vol. 6, Apr. 2010Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Microelectronic Systems Lab. (LSM)Ecole Polytechnique Fédérale de Lausanne (EPFL)LausanneSwitzerland

Personalised recommendations