Low-Activity-Rate and Memory Circuits in STSCL



As already discussed in Chap. 3, reduced voltage swing, fast current domain switching speed, and fully differential topology of SCL circuits make them very suitable for high frequency applications. In addition, SCL circuits exhibit very low sensitivity to common-mode noise sources with very low noise injection to substrate or supply lines [1,2]


Supply Voltage Voltage Swing Static Random Access Memory CMOS Circuit Memory Circuit 
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  1. 1.
    S. Badel, “MOS current-mode logic standard cells for high-speed low-noise applications,” PhD Dissertation, Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 2008Google Scholar
  2. 2.
    P. Heydari and R. Mohanavelu, “Design of ultrahigh-speed low-voltage CMOS CML buffers and latches,” in IEEE Tranactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1081–1093, Oct. 2004Google Scholar
  3. 3.
    A. Tajalli, P. Muller, and Y. Leblebici, “A power-efficient clock and data recovery circuit in 0.18-μm CMOS technology for multi-channel short-haul optical data communication,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2235–2244, Oct. 2007Google Scholar
  4. 4.
    J. M. Musicer and J. Rabaey, “MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environment,” in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 102–107, 2000Google Scholar
  5. 5.
    M. Pedram and J. Rabaey, Power Aware Design Methodologies, Kluwer, 2002Google Scholar
  6. 6.
    A. Tajalli, E. Vittoz, Y. Leblebici, and E. J. Brauer, “Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept,” in Proceedings of European Solid-State Ciruits Conference (ESSCIRC), Munich, Germany, pp. 281–284, Sep. 2007Google Scholar
  7. 7.
    A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz, “Sub-threshold source-coupled logic circuit design for ultra low power applications,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1699–1710, Jul. 2008Google Scholar
  8. 8.
    S. -M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, McGraw-Hill, 2003Google Scholar
  9. 9.
    B. Nikolic̀, “Design in the power-limited scaling regime,” in IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 71–83, Jan. 2008Google Scholar
  10. 10.
    B. H. Calhoun, and A. Chandrakasan, “Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering,” IEEE J. Solid-State Circuits, vol. 41, pp. 238–245, Jan. 2006Google Scholar
  11. 11.
    B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200 mV 6-T subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338–2348, Oct. 2008Google Scholar
  12. 12.
    B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680–688, Mar. 2007Google Scholar
  13. 13.
    N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy,” J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008Google Scholar
  14. 14.
    C. Y. Lu and J. M. Sung, “Reverse short-channel effects on threshold voltage in submicrometer salicide devices,” in IEEE Electron Device Letters, vol. 10, no. 10, pp. 446–448, Oct. 1989Google Scholar
  15. 15.
    C. Subramanian, “Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs,” in International Electron Device Meeting, pp. 423–426, Dec. 1995Google Scholar
  16. 16.
    T. -H. Kim, J. Liu, J. Keane, and C. H. Kim, “A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltagre computating,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 518–529, Feb. 2008Google Scholar
  17. 17.
    J. P. Kulkarni, K. Kim, K. Roy, “A 160 mV robust Schmitt triger based subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303–2313, Oct. 2007Google Scholar
  18. 18.
    I. J. Chang, J. -J. Kim, S. P. Park, and K. Roy, “A 32 kb 10 T sub-threshold SRAM array with bit-inteleaved and differential read scheme in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650–658, Feb. 2009Google Scholar
  19. 19.
    Y. Wang, et al., “A 1.1 GHz 12 μA/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 172–179, Jan. 2008Google Scholar
  20. 20.
    A. Tajalli and Y. Leblebici, “Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems,” to apear in European Solid-State Circuits Conference (ESSCIRC), Sep. 2009Google Scholar
  21. 21.
    C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor Modeling, Wiley, 2006Google Scholar

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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Microelectronic Systems Lab. (LSM)Ecole Polytechnique Fédérale de Lausanne (EPFL)LausanneSwitzerland

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