Subthreshold Source-Coupled Logic Performance Analysis



Unlike conventional digital CMOS circuits where there is no static power consumption (neglecting the leakage current), in source-coupled logic (SCL) topology each cell consumes a specifc amount of constant bias current. During each transition, this current is charging or discharging the load capacitance. Hence, more static bias current directly translates into faster transitions at the output nodes of an SCL circuit. When there is no transition at the input of an SCL gate, on the other hand, the static bias current of the gate is only used to preserve the output voltage levels on the desired values. Therefore, there is specifc amount of static power consumption even during static operating conditions which is not used for processing purpose. Regarding that, as the circuit activity rate or duty rate reduces, the power effciency of SCL topology degrades quickly. Under these conditions where the activity rate is low, CMOS circuits can over a better power compromise


Bias Current Full Adder Delay Product Static Power Consumption Logic Depth 


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  1. 1.
    M. Pedram and J. Rabaey, Power Aware Design Methodologies, Kluwer, 2002Google Scholar
  2. 2.
    H. Soeleman, K. Roy, and B. C. Paul, “Robust subthreshold logic for ultra-low power operation,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 90–99, Feb. 2001Google Scholar
  3. 3.
    B. Nikolic̀, “Design in the power-limited scaling regime,” in IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 71–83, Jan. 2008Google Scholar
  4. 4.
    B. H. Calhoun, and A. Chandrakasan, “Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering,” IEEE J. Solid-State Circuits, vol. 41, pp. 238–245, Jan. 2006Google Scholar
  5. 5.
    M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits, Managing Leakage Power, Kluwer, 2003Google Scholar
  6. 6.
    N. Verma, J. Kwong, and A. Chandrakasan, “Nanometer MOSFET variation in minimum energy subthreshold circuits,” in IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 163–174, Jan. 2008Google Scholar
  7. 7.
    E. Alon and M. Horowitz, “Integrated regulation for energy-efficient digital circuits,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1795–1807, Aug. 2008Google Scholar
  8. 8.
    A. Tajalli, E. Vittoz, Y. Leblebici, and E.J. Brauer, “Ultra low power subthreshold current mode logic utilizing a novel PMOS load device,” in IEE Electronics Letters, vol. 43, no. 17, pp. 911–913, Aug. 2007Google Scholar
  9. 9.
    A. Tajalli, E. Vittoz, Y. Leblebici, and E. J. Brauer, “Ultra-low power subthreshold current-mode logic ulitising PMOS load device concept,” IET Electronics Letters, vol. 43, no. 17, pp. 911–913, Aug. 2007Google Scholar
  10. 10.
    S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, McGraw-Hill, 2003Google Scholar
  11. 11.
    C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor Modeling, Wiley, 2006Google Scholar
  12. 12.
    P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Wiely, Fourth Ed., 2000Google Scholar
  13. 13.
    S. Badel, “MOS current-mode logic standard cells for high-speed low-noise applications,” PhD Dissertation, Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 2008Google Scholar
  14. 14.
    M. Mizuno, and et al., “A GHz MOS adaptive pipeline technique using MOS current-mode logic,” IEEE J. Solid-State Circuits, pp. 784–791, vol. 31, no. 6, Jun. 1996Google Scholar
  15. 15.
    J. M. Musicer and J. Rabaey, “MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environment,” in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 102–107, 2000Google Scholar
  16. 16.
    A. Tajalli, F. K. Gurkaynak, Y. Leblebici, M. Alioto, and E. J. Brauer, “Improving the power–delay product in SCL circuits using source follower output stage,” in Proceedings of International Symposium on Circuits and Systems (ISCAS), pp. 145–148, Seattle, USA, May 2008Google Scholar
  17. 17.
    A. Tajalli, M. Alioto, and Y. Leblebici, “Power–delay performance improvement of subthreshold SCL circuits,” in IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 56, no. 2, pp. 127–131, Feb. 2009Google Scholar
  18. 18.
    A. Tajalli, E. J. Brauer, and Y. Leblebici, “Ultra low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP,” Elsevier Microelectron. J., vol. 40, no. 6, pp. 973–978, Jun. 2009Google Scholar

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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Microelectronic Systems Lab. (LSM)Ecole Polytechnique Fédérale de Lausanne (EPFL)LausanneSwitzerland

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