Skip to main content
SpringerLink
Log in

ASPA: Asynchronous–Synchronous Focal-Plane Sensor-Processor Chip

  • Chapter
  • First Online:
Focal-Plane Sensor-Processor Chips

Abstract

This chapter describes the architecture and implementation of a digital vision chip, with asynchronous processing capabilities (asynchronous/synchronous processor array or ASPA). The discussion focuses on design aspects of cellular processor array with compact digital processing cell suitable for parallel image processing. The presented vision chip is based on an array of processing cells, each incorporating photo-sensor with a one-bit ADC and simple digital processor, which consists of 64-bit memory, arithmetic and logic unit (ALU), flag register and communication unit. The chip has two modes of operation: synchronous mode for local and nearest-neighbour operations and continuous-time mode for global operations. The speed of global image processing operations is significantly increased by using asynchronous processing techniques. In addition, the periphery circuitry enables asynchronous address extraction, fixed pattern addressing and flexible random access data I/O.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. G. M. Amdahl, Validity of the single-processor approach to achieving large-scale computing capabilities, in Proceedings of American Federation of Information Processing Societies Conference, pp. 483–485, 1967

    Google Scholar 

  2. M. J. B. Duff and D. M. Watson, The cellular logic array image processor, Computer Journal, 20, 68–72, 1977/02/ 1977

    Google Scholar 

  3. K. E. Batcher, Design of a massively parallel processor, IEEE Transactions on Computers, c-29, 836–840, 1980

    Google Scholar 

  4. K. Aizawa, Computational sensors-vision VLSI, IEICE Transactions on Information and Systems, E82-D, 580–588, 1999

    Google Scholar 

  5. A. Moini, Vision Chips or Seeing Silicon, Kluwer, Dordrecht, 1999

    Google Scholar 

  6. A. A. Abbo, R. P. Kleihorst, V. Choudhary, L. Sevat, P. Wielage, S. Mouy, B. Vermeulen, and M. Heijligers, Xetal-II: A 107 GOPS, 600 mW massively parallel processor for video scene analysis, IEEE Journal of Solid-State Circuits, 43, 192–201, 2008

    Article  Google Scholar 

  7. L. Lindgren, J. Melander, R. Johansson, and B. Moller, A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging, IEEE Journal of Solid-State Circuits, 40, 1350–1359, 2005

    Article  Google Scholar 

  8. P. Dudek and P. J. Hicks, A general-purpose processor-per-pixel analogue SIMD vision chip, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 52, 13–20, 2005/01/2005

    Google Scholar 

  9. T. Komuro, I. Ishii, M. Ishikawa, and A. Yoshida, A digital vision chip specialized for high-speed target tracking, IEEE Transactions on Electron Devices, 50, 191–199, 2003

    Article  Google Scholar 

  10. G. C. Linan, A. Rodriguez-Vazquez, R. C. Galan, F. Jimenez-Garrido, S. Espejo, and R. Dominguez-Castro, A 1000 FPS at 128 x128 vision processor with 8-bit digitized I/O, IEEE Journal of Solid-State Circuits, 39, 1044–1055, 2004

    Google Scholar 

  11. A. Lopich and P. Dudek, Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array, International Journal of Circuit Theory and Applications, Article first published online: 29 Apr 2010, DOI: 10.1002/cta.679, 2011

    Google Scholar 

  12. R. Forchheimer and A. Odmark, A single chip linear array picture processor, Proceedings of the SPIE – The International Society for Optical Engineering, 397, 425–430, 1983

    Google Scholar 

  13. K. Chen, M. Afghahi, P. E. Danielsson, and C. Svensson, PASIC: A processor-A/D converter-sensor integrated circuit, in Proceedings – IEEE International Symposium on Circuits and Systems, New Orleans, LA, USA, 1990, pp. 1705–1708

    Google Scholar 

  14. K. Chen and C. Svensson, A 512-processor array chip for video/image processing, in From Pixels to Features II. Parallelism in Image Processing. Proceedings of a Workshop, Amsterdam, The Netherlands, 1991, pp. 187–199

    Google Scholar 

  15. M. Gokstorp and R. Forchheimer, Smart vision sensors, in IEEE International Conference on Image Processing, Chicago, IL, USA, 1998, pp. 479–482

    Google Scholar 

  16. D. Andrews, C. Kancler, and B. Wealand, An embedded real-time SIMD processor array for image processing, in Proceedings of the 4th International Workshop on Parallel and Distributed Real-Time Systems, Los Alamitos, USA, 1996, pp. 131–134

    Google Scholar 

  17. J. C. Gealow and C. G. Sodini, Pixel-parallel image processor using logic pitch-matched to dynamic memory, IEEE Journal of Solid-State Circuits, 34, 831–839, 1999

    Article  Google Scholar 

  18. R. P. Kleihorst, A. A. Abbo, A. van der Avoird, M. J. R. Op de Beeck, L. Sevat, P. Wielage, R. van Veen, and H. van Herten, Xetal: A low-power high-performance smart camera processor, in IEEE International Symposium on Circuits and Systems, NJ, USA, 2001, pp. 215–218

    Google Scholar 

  19. J.-E. Eklund, C. Svensson, and A. Astrom, VLSI implementation of a focal plane image processor – a realization of the near-sensor image processing concept, IEEE Transaction on VLSI Systems, 4, 322–335, 1996

    Article  Google Scholar 

  20. J. Poikonen, M. Laiho, and A. Paasio, MIPA4k: A 64 ×64 cell mixed-mode image processor array, in IEEE International Symposium on Circuits and Systems Taiwan, 2009, pp. 1927–1930

    Google Scholar 

  21. F. Paillet, D. Mercier, and T. M. Bernard, Second generation programmable artificial retina, in Twelfth Annual IEEE International ASIC/SOC Conference, 15–18 Sept. 1999, Washington, DC, USA, 1999, pp. 304–309

    Google Scholar 

  22. M. Wei, L. Qingyu, Z. Wancheng, and W. Nan-Jian, A programmable SIMD vision chip for real-time vision applications, IEEE Journal of Solid-State Circuits, 43, 1470–1479, 2008

    Article  Google Scholar 

  23. T. Komuro, S. Kagami, and M. Ishikawa, A dynamically reconfigurable SIMD processor for a vision chip, IEEE Journal of Solid-State Circuits, 39, 265–268, 2004

    Article  Google Scholar 

  24. V. Gies, T. M. Bernard, and A. Merigot, Convergent micro-pipelines: A versatile operator for mixed asynchronous-synchronous computations, in IEEE International Symposium on Circuits and Systems (ISCAS), NJ, USA, 2005, pp. 5242–5245

    Google Scholar 

  25. M. Arias-Estrada, M. Tremblay, and D. Poussart, A focal plane architecture for motion computation, Real-Time Imaging, 2, 351–360, 1996

    Article  Google Scholar 

  26. B. Ducourthial and A. Merigot, Parallel asynchronous computations for image analysis, Proceedings of the IEEE, 90, 1218–1229, 2002

    Article  Google Scholar 

  27. F. Robin, G. Privat, and M. Renaudin, Asynchronous relaxation of morphological operators: A joint algorithm-architecture perspective, International Journal of Pattern Recognition and Artificial Intelligence, 11, 1085–1094, 1997

    Article  Google Scholar 

  28. F. Robin, M. Renaudin, and G. Privat, An asynchronous 16 ×16 pixel array-processor for morphological filtering of greyscale images, in European Solid-State Circuits Conference, Gif-sur-Yvette, France, 1996, pp. 188–191

    Google Scholar 

  29. A. Lopich and P. Dudek, Hardware implementation of skeletonization algorithm for parallel asynchronous image processing, Journal of Signal Processing Systems, 56, 91–103, 2009

    Article  Google Scholar 

  30. B. Galilee, F. Mamalet, M. Renaudin, and P. Y. Coulon, Parallel asynchronous watershed algorithm-architecture, IEEE Transactions on Parallel and Distributed Systems, 18, 44–56, 2007

    Article  Google Scholar 

  31. D. Noguet, Massively parallel implementation of the watershed based on cellular automata, in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Zurich, Switzerland, 1997, pp. 42–52

    Google Scholar 

  32. P. Dudek, A flexible global readout architecture for an analogue SIMD vision chip, in IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, 2003, pp. 782–785

    Google Scholar 

  33. K. A. Zaghloul and K. Boahen, Optic nerve signals in a neuromorphic chip I&II, IEEE Transactions on Biomedical Engineering, 51, 657–666, 2004

    Article  Google Scholar 

  34. D. L. Vilarino, V. M. Brea, D. Cabello, and J. M. Pardo, Discrete-time CNN for image segmentation by active contours, Pattern Recognition Letters, 19, 721–734, 1998

    Article  MATH  Google Scholar 

  35. A. Kitchen, A. Bermak, and A. Bouzerdoum, A digital pixel sensor array with programmable dynamic range, IEEE Transactions on Electron Devices, 52, 2591–2601, 2005

    Article  Google Scholar 

  36. A. Lopich and P. Dudek, An 80 ×80 general-purpose digital vision chip in 0.18 um CMOS technology, in IEEE International Symposium on Circuits and Systems, Paris, France, 2010, pp. 4257–4260

    Google Scholar 

  37. A. Lopich and P. Dudek, Global operations in SIMD cellular processor arrays employing functional asynchronism, in IEEE International Workshop on Computer Architecture for Machine Perception and Sensing, Montreal, Canada, 2007, pp. 16–23

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Manchester, Manchester, M13 9PL, UK

    Piotr Dudek

Authors
  1. Alexey Lopich
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Piotr Dudek
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Piotr Dudek .

Editor information

Editors and Affiliations

  1. Computer & Automation Research Inst., MTA Budapest, Budapest, 1518, Hungary

    Ákos Zarándy

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Lopich, A., Dudek, P. (2011). ASPA: Asynchronous–Synchronous Focal-Plane Sensor-Processor Chip. In: Zarándy, Á. (eds) Focal-Plane Sensor-Processor Chips. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6475-5_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6475-5_4

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-6474-8

  • Online ISBN: 978-1-4419-6475-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation