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MIPA4k: Mixed-Mode Cellular Processor Array

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Focal-Plane Sensor-Processor Chips

Abstract

This chapter describes MIPA4k, a 64 ×64 cell mixed-mode image processor array chip. Each cell includes an image sensor, A/D/A conversion, embedded digital and analog memories, and hardware-optimized grey-scale and binary processing cores. We describe the architecture of the processor cell, go through the different functional blocks and explore its processing capabilities. The processing capabilities of the cells include programmable space-dependent neighbourhood connections, ranked-order filtering, rank identification and anisotropic resistive filtering. For example, asynchronous analog morphological reconstruction operation can be performed with MIPA4k. The image sensor has an option for locally adaptive exposure time. Also, the peripheral circuitry can highlight windows of activation, and pattern matching can be performed on these regions of interest (ROI) with the aid of parallel write operation to the active window. As the processing capabilities are complemented with global OR and global sum operations, MIPA4k is an effective tool for high-speed image analysis.

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References

  1. L.O. Chua, L. Yang, Cellular Neural Networks: Theory, IEEE Transactions on Circuits and Systems-I, vol. 35, no. 10, pp. 1257–1272, October 1988

    MathSciNet  MATH  Google Scholar 

  2. A. Rodriguez-Vazquez, G. Linan-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galan, F. Jimenez-Garrido, R. Dominguez-Castro, S.E. Meana, ACE16k: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51, no. 5, pp. 851–863, 2004

    Article  Google Scholar 

  3. P. Dudek, P.J. Hicks, A General-Purpose Processor-per-Pixel Analog SIMD Vision Chip, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 52, no. 1, pp. 13–20, 2005

    Article  Google Scholar 

  4. P. Dudek, Implementation of SIMD Vision Chip with 128 × 128 Array of Analogue Processing Elements, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2005, vol. 6, pp. 5806–5809, 2005

    Google Scholar 

  5. A. Lopich, P. Dudek, Architecture of a VLSI Cellular Processor Array for Synchronous/ Asynchronous Image Processing, Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp. 3618–3621, 2006

    Google Scholar 

  6. A. Lopich, P. Dudek, ASPA: Focal Plane Digital Processor Array with Asynchronous Processing Capabilities, Proceedings of the 2008 IEEE International Symposium on Circuits and Systems, pp. 1592–1595, 2008

    Google Scholar 

  7. C. Rekeczky, T. Roska, A. Ushida, CNN-Based Difference-Controlled Adaptive Nonlinear Image Filters, International Journal on Circuit Theory and Applications, 26, pp. 375–423, 1998

    Article  MATH  Google Scholar 

  8. C. Rekeczky, A. Tahy, Z. Vegh, T. Roska, CNN-based Spatio-Temporal Nonlinear Filtering and Endocardial Boundary Detection in Echocardiography, International Journal of Circuit Theory and Applications, vol. 27, pp. 171–207, 1999

    Article  Google Scholar 

  9. A. Paasio, A. Kananen, M. Laiho, K. Halonen, A Compact Computational Core for Image Processing, Proceedings of the European Conference on Circuit Theory and Design, ECCTD’01, pp. I-337–I-339, 2001

    Google Scholar 

  10. A. Paasio, A. Kananen, M. Laiho, K. Halonen, An Analog Array Processor Hardware Realization with Multiple New Features, Proceedings of the International Joint Conference on Neural Networks, IJCNN, pp. 1952–1955, 2002

    Google Scholar 

  11. J. Poikonen, M. Laiho, A. Paasio, MIPA4k: A 64 × 64 Cell Mixed-Mode Image Processor Array, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS2009, pp. 1927–1930, Taipei 2009

    Google Scholar 

  12. M. Laiho, A. Paasio, J. Flak, K. Halonen, Template Design for Cellular Nonlinear Networks With 1-Bit Weights, IEEE Transactions on Circuits and Systems I, vol. 55, no. 3, pp. 904–913, 2008

    Article  MathSciNet  Google Scholar 

  13. M. Laiho, J. Poikonen, A. Paasio, Space-Dependent Image Processing Within a 64 × 64 Mixed-Mode Array Processor, IEEE International Workshop on Cellular Nanoscale Networks and Applications, Berkeley, 2010

    Google Scholar 

  14. M. Laiho, J. Poikonen, A. Paasio, Object Segmentation and Tracking with Asynchronous Grayscale and Binary Wave Operations on the MIPA4k, European Conference on Circuit Theory and Design, Antalya, 2009

    Google Scholar 

  15. M. Laiho, J. Poikonen, A. Paasio, K. Halonen, Centroiding and Classification of Objects Using a Processor Array with a Scalable Region of Interest, IEEE International Symposium on Circuits and System, Seattle, pp. 1604–1607, 2008

    Google Scholar 

  16. J. Poikonen, M. Laiho, A. Paasio, Locally Adaptive Image Sensing with the 64 × 64 Cell MIPA4k Mixed-Mode Image Processor Array, European Conference on Circuit Theory and Design, Antalya, 2009

    Google Scholar 

  17. J. Poikonen, A. Paasio, A Ranked Order Filter Implementation for Parallel Analog Processing, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 5, pp. 974–987, 2004

    Article  Google Scholar 

  18. J. Poikonen, A. Paasio, Rank Identification for an Analog Ranked Order Filter, Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, ISCAS 2005, vol. 3, pp. 2819–2822, 2005

    Google Scholar 

  19. J. Poikonen, A. Paasio, An 8 × 8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13μm CMOS, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1541–1553, 2009

    Article  MathSciNet  Google Scholar 

  20. J. Poikonen, Absolute Value Extraction and Order Statistic Filtering for a Mixed-Mode Array Image Processor, Doctoral thesis, Turku Centre for Computer Science (TUCS) Dissertations, no. 80, November 2006

    Google Scholar 

  21. J. Poikonen, A. Paasio, Current Controlled Resistive Fuse Implementation in a Mixed-Mode Array Processor Core, Proceedings Of the 8th IEEE International Workshop on Cellular Neural Networks and their Applications, pp. 76–81, 2004

    Google Scholar 

  22. L. Vesalainen, J. Poikonen, A. Paasio, A Fuzzy Unit for a Mixed-Mode Array Processor, Proceedings of the 8th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2004, pp. 273–278, 2004

    Google Scholar 

  23. J. Poikonen, M. Laiho, A. Paasio, Anisotropic Filtering with a Resistive Fuse Network on the MIPA4k Processor Array, IEEE International Workshop on Cellular Nanoscale Networks and Applications, Berkeley, 2010

    Google Scholar 

  24. B.E. Shi, Order Statistic Filtering with Cellular Neural Networks, Proceedings of the 3rd IEEE International Workshop on Neural Networks and their Applications, CNNA-94, pp. 441–443, 1994

    Google Scholar 

  25. A. Zarandy, A. Stoffels, T. Roska, L.O. Chua, Implementation of Binary and Gray-Scale Mathematical Morphology on the CNN Universal Machine, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 45, no. 2, pp. 163–168, 1998

    Article  Google Scholar 

  26. I.E. Opris, Analog Rank Extractors and Sorting Networks, Ph.D. Thesis, Stanford University, 1996

    Google Scholar 

  27. L. Vincent, Morphological Grayscale Reconstruction in Image Analysis: Applications and Efficient Algorithms, IEEE Transactions on Image Processing, vol. 2, no. 2, pp. 176–200, 1993

    Article  Google Scholar 

  28. J. Poikonen, A. Paasio, An Area-Efficient Full-Wave Current Rectifier For Analog Array Processing, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003, vol. 5, pp. 757–760, 2003

    Google Scholar 

  29. P. Perona, J. Malik, Scale-Space and Edge Detection Using Anisotropic Diffusion, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 12, no. 7, pp. 629–639, 1990

    Article  Google Scholar 

  30. A. Blake, A. Zisserman, Visual Reconstruction, MIT, Cambridge, MA, 1987

    Google Scholar 

  31. J. Schlemmel, K. Meier, M. Loose, A Scalable Switched Capacitor Realization of the Resistive Fuse Network, Analog Integrated Circuits and Signal Processing, 32, pp. 135–148, 2002

    Article  Google Scholar 

  32. P. Yu, S. Decker, H. Lee, C. Sodini, J. Wyatt, Resistive Fuses for Image Smoothing and Segmentation, IEEE Journal of Solid-State Circuits, vol. 2, pp. 894–898, 1992

    Google Scholar 

  33. P. Acosta-Serafini et al., A 1/3 VGA Linear Wide Dynamic Range CMOS Image Sensor Implementing Predictive Multiple Sampling Algorithm With Overlapping Integration Intervals, IEEE Journal of Solid State Circuits, pp. 1487–1496, 2004

    Google Scholar 

  34. C. Posch et al., An Asynchronous Time-Based Image Sensor, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp. 2130–2133, 2008

    Google Scholar 

  35. A. Zarandy et al., Per Pixel Integration Time Controlled Image Sensor, European Conference on Circuit Theory and Design, pp. III/149–III/152, 2005

    Google Scholar 

  36. C.M. Dominguez-Matas et al., 3-Layer CNN Chip for Focal-Plane Complex Dynamics with Adaptive Image Capture, IEEE International Workshop on Cellular Neural Networks and their Applications, pp. 340–345, 2006

    Google Scholar 

  37. R. Carmona et al., A CNN-Driven Locally Adaptive CMOS Image Sensor, IEEE International Symposium on Circuits and Systems, ISCAS’04, vol. V, pp. 457–460, Vancouver, 2004

    Google Scholar 

  38. M. Laiho, J. Poikonen, K. Virtanen, A. Paasio, Self-adapting Compressive Image Sensing Scheme, IEEE International Workshop on Cellular Neural Networks and their Applications, pp. 125–128, 2008

    Google Scholar 

  39. V. Brajovic, Brightness Perception, Dynamic Range and Noise: A Unifying Model for Adaptive Image Sensors, IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2004

    Google Scholar 

  40. M. Laiho, V. Brea, A. Paasio, Effect of Mismatch on the Reliability of ON/OFF Programmable CNNs, IEEE Transactions on Circuits and Systems-I, vol. 56, no. 10, pp. 2259–2269, October 2009

    Article  MathSciNet  Google Scholar 

  41. T. Roska et al., CNN Software Library, Version 1.1, Analogical and Neural Computing Laboratory, Hungarian Academy of Sciences, 2000, http://lab.analogic.sztaki.hu/Candy/csl.html

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Acknowledgements

This work was partly funded by the Academy of Finland grants 106451, 117633 and 131295. The authors also thank Turku Science Park and The Turku University Foundation for their help in funding the MIPA4k chip manufacturing.

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Correspondence to Mika Laiho .

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Laiho, M., Poikonen, J., Paasio, A. (2011). MIPA4k: Mixed-Mode Cellular Processor Array. In: Zarándy, Á. (eds) Focal-Plane Sensor-Processor Chips. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6475-5_3

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  • DOI: https://doi.org/10.1007/978-1-4419-6475-5_3

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