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SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array

Chapter

Abstract

In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW.

Keywords

Processing Element Single Instruction Multiple Data Processor Array Image Processing Operation Processing Element Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgement

This work has been supported by the EPSRC; grant numbers: EP/D503213 and EP/D029759. The author thanks Dr Stephen Carey and Dr David Barr for their contributions to testing and system development for the SCAMP-3 device.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.The University of ManchesterManchesterUK

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