Low Power Graphics Processors

  • Preeti Ranjan Panda
  • Aviral Shrivastava
  • B. V. N. Silpa
  • Krishnaiah Gummidipudi


So far we studied power optimizations at various levels of design abstraction such as the circuit level, architectural level, all the way up to the server and data center level. In this chapter, we present a case study that combines several of the aforementioned techniques in a reasonably complex system: a power efficient Graphics Processor.


Current Frame Proportional Integral Derivative Proportional Integral Derivative Controller Graphic Processor Texture Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
  2. 2.
    Barrio, V.M.D., González, C., Roca, J., Fernández, A., Espasa, R.: A single (unified) shader gpu microarchitecture for embedded systems. In: HiPEAC, pp. 286–301 (2005)Google Scholar
  3. 3.
    Chen, C.H., Lee, C.Y.: Two-level hierarchical Z-buffer for 3D graphics hardware. In: Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, vol. 2, pp. II–253–II–256 vol.2 (2002)Google Scholar
  4. 4.
    Choi, K., Soma, R., Pedram, M.: Off-chip latency-driven dynamic voltage and frequency scaling for an mpeg decoding. In: DAC ’04: Proceedings of the 41st annual Design Automation Conference, pp. 544–549. ACM, New York, NY, USA (2004). DOI http://doi.acm.org/10.1145/996566.996718 CrossRefGoogle Scholar
  5. 5.
    Chung, K., Yu, C.H., Kim, L.S.: Vertex cache of programmable geometry processor for mobile multimedia application. In: Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp. 4 pp.– (2006). DOI 10.1109/ISCAS.2006.1692983Google Scholar
  6. 6.
    Flautner, K., Mudge, T.: Vertigo: automatic performance-setting for linux. SIGOPS Oper. Syst. Rev. 36(SI), 105–116 (2002). DOI http://doi.acm.org/10.1145/844128.844139 CrossRefGoogle Scholar
  7. 7.
    Greene, N., Kass, M., Miller, G.: Hierarchical Z-buffer visibility. In: SIGGRAPH ’93: Proceedings of the 20th annual conference on Computer graphics and interactive techniques, pp. 231–238. ACM, New York, NY, USA (1993). DOI http://doi.acm.org/10.1145/166117.166147 CrossRefGoogle Scholar
  8. 8.
    Gu, Y., Chakraborty, S.: Control theory-based dvs for interactive 3D games. In: DAC ’08: Proceedings of the 45th annual Design Automation Conference, pp. 740–745. ACM, New York, NY, USA (2008). DOI http://doi.acm.org/10.1145/1391469.1391659 CrossRefGoogle Scholar
  9. 9.
    Gu, Y., Chakraborty, S.: Power management of interactive 3D games using frame structures. In: VLSI Design, 2008. VLSID 2008. 21st International Conference on, pp. 679–684 (2008). DOI 10.1109/VLSI. 2008.102Google Scholar
  10. 10.
    Gu, Y., Chakraborty, S., Ooi, W.T.: Games are up for dvfs. In: Design Automation Conference, 2006 43rd ACM/IEEE, pp. 598–603 (2006). DOI 10.1109/DAC.2006.229295Google Scholar
  11. 11.
    Hakura, Z.S., Gupta, A.: The design and analysis of a cache architecture for texture mapping. SIGARCH Comput. Archit. News 25(2), 108–120 (1997). DOI http://doi.acm.org/10.1145/384286.264152 CrossRefGoogle Scholar
  12. 12.
    Hasselgren, J., Akenine-Möller, T.: Efficient depth buffer compression. In: GH ’06: Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware, pp. 103–110. ACM, New York, NY, USA (2006). DOI http://doi.acm.org/10.1145/1283900.1283917 CrossRefGoogle Scholar
  13. 13.
    Hoppe, H.: Optimization of mesh locality for transparent vertex caching. In: SIGGRAPH ’99: Proceedings of the 26th annual conference on Computer graphics and interactive techniques, pp. 269–276. ACM Press/Addison-Wesley Publishing Co., New York, NY, USA (1999). DOI http://doi.acm.org/10.1145/311535.311565 CrossRefGoogle Scholar
  14. 14.
    Iourcha, K.I., Nayak, K.S., Hong, Z.: System and method for fixed-rate block-based image compression with inferred pixel values. Patent 5956431 (1999). Http://www.freepatentsonline.com/5956431.html
  15. 15.
    Lu, Z., Hein, J., Humphrey, M., Stan, M., Lach, J., Skadron, K.: Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. In: CASES ’02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 156–163. ACM, New York, NY, USA (2002). DOI http://doi.acm.org/10.1145/581630.581654 CrossRefGoogle Scholar
  16. 16.
    McCormack, J., McNamara, R.: Tiled polygon traversal using half-plane edge functions. In: HWWS ’00: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, pp. 15–21. ACM, New York, NY, USA (2000). DOI http://doi.acm.org/10.1145/346876.346882 CrossRefGoogle Scholar
  17. 17.
    Mochocki, B.C., Lahiri, K., Cadambi, S., Hu, X.S.: Signature-based workload estimation for mobile 3D graphics. In: DAC ’06: Proceedings of the 43rd annual Design Automation Conference, pp. 592–597. ACM, New York, NY, USA (2006). DOI http://doi.acm.org/10.1145/1146909.1147062 CrossRefGoogle Scholar
  18. 18.
    Möller, T., Haines, E.: Real-time rendering. A. K. Peters, Ltd., Natick, MA, USA (1999)Google Scholar
  19. 19.
    Park, W.C., Lee, K.W., Kim, I.S., Han, T.D., Yang, S.B.: A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. In: Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on, pp. 173–182 (2002). DOI 10.1109/ASAP.2002.1030717Google Scholar
  20. 20.
    Rasmusson, J., Strom, J., Akenine-Moller, T.: Error-bounded lossy compression of floating-point color buffers using quadtree decomposition. Vis. Comput. 26(1), 17–30 (2009). DOI http://dx.doi.org/10.1007/s00371-009-0372-y CrossRefGoogle Scholar
  21. 21.
    Silpa, B., Kumar S.S, V., Panda, P.R.: Adaptive partitioning of vertex shader for low power high performance geometry engine. In: Advances in Visual Computing, Lecture Notes in Computer Science, vol. 5875/2009, pp. 111–124. Springer Berlin / Heidelberg (2009). DOI 10.1007/978-3-642-10331-5∖{ _}11Google Scholar
  22. 22.
    Silpa, B.V.N., Patney, A., Krishna, T., Panda, P.R., Visweswaran, G.S.: Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. In: ICCAD ’08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 559–564. IEEE Press, Piscataway, NJ, USA (2008)Google Scholar
  23. 23.
    Tan, Y., Malani, P., Qiu, Q., Wu, Q.: Workload prediction and dynamic voltage scaling for mpeg decoding. In: ASP-DAC ’06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference, pp. 911–916. IEEE Press, Piscataway, NJ, USA (2006). DOI http://doi.acm.org/10.1145/1118299.1118505
  24. 24.
    Wang, P.H., Chen, Y.M., Yang, C.L., Cheng, Y.J.: A predictive shutdown technique for gpu shader processors. IEEE Computer Architecture Letters 8, 9–12 (2009). DOI http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.1 CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Preeti Ranjan Panda
    • 1
  • Aviral Shrivastava
    • 2
  • B. V. N. Silpa
    • 1
  • Krishnaiah Gummidipudi
    • 1
  1. 1.Department Computer Science and EngineeringIndian Institute of TechnologyNew DelhiIndia
  2. 2.Department of Computer Science and EngineeringArizona State UniversityTempeUSA

Personalised recommendations