Integrated Modeling using Finite State Machines and Dataflow Graphs

  • Joachim Falk
  • Joachim Keinert
  • Christian Haubelt
  • Jürgen Teich
  • Christian Zebelein


In this chapter, different application modeling approaches based on the integration of finite state machines with dataflow models are reviewed. A particular focus is put on the analyzability of these models and the way how restricted Models of Computation are exploited in design methodologies to optimize the hardware/- software implementation of a given application model.


Output Port Finite State Machine Input Port Static Schedule Hasse Diagram 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Balarin, F., Giusto, P., Jurecska, A., Passerone, C., Sentovich, E., Tabbara, B., Chiodo, M., Hsieh, H., Lavagno, L., Sangiovanni-Vincentelli, A., Suzuki, K.: Hardware-Software Co- Design of Embedded Systems: The POLIS Approach. Kluwer Academic Publishers (1997)MATHGoogle Scholar
  2. 2.
    Beux, S.L.: Un flot de conception pour applications de traitement du signal systématique implémentées sur fpga à base d’ingénierie dirigée par les modèles. Ph.D. thesis, Université des Sciences et Technologies de Lille (2007)Google Scholar
  3. 3.
    Bhattacharyya, S., Brebner, G., Eker, J., Mattavelli, M., Raulet, M.: OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems (2008). First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27–28, 2008Google Scholar
  4. 4.
    Bhattacharyya, S.S., Buck, J.T., Ha, S., Lee, E.A.: Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 42(3), 138–150 (1995)MATHCrossRefGoogle Scholar
  5. 5.
    Buck, J., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems. International Journal in Computer Simulation 4(2), 155–182 (1994)Google Scholar
  6. 6.
    Buck, J.T.: Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. Tech. rep., Dept. of EECS, UC Berkeley, Berkeley, CA 94720, U.S.A. (1993). Technical Report UCB/ERL 93/69, Ph.D dissertationGoogle Scholar
  7. 7.
    Dennis, J.B.: First version of a data flow procedure language. In: Programming Symposium, Proceedings Colloque sur la Programmation, pp. 362–376. Springer-Verlag, London, UK (1974)Google Scholar
  8. 8.
    Dumont, P., Boulet, P.: Another multidimensional synchronous dataflow: Simulating Array- OL in Ptolemy II. Tech. Rep. 5516, Institut National de Recherche en Informatique et en Automatique, Cité Scientifique, 59 655 Villeneuve d’Ascq Cedex (2005)Google Scholar
  9. 9.
    Ecker, J., Janneck, J.W.: Cal language report - language version 1.0. Tech. rep., University of California at Berkeley (2003).Google Scholar
  10. 10.
    Ecker, J., Janneck, J.W.: (2009)
  11. 11.
    Eker, J., Janneck, J.W., Lee, E.A., Liu, J., Liu, X., Ludvig, J., Neuendorffer, S., Sachs, S., Xiong, Y.: Taming heterogeneity - the Ptolemy approach. In: Proceedings of the IEEE (2002).Google Scholar
  12. 12.
    Falk, J., Haubelt, C., Teich, J.: Efficient Representation and Simulation of Model-Based Designs in SystemC. Proc. FDL’06, Forum on Design Languages 2006, pp. 129 - 134. Darmstadt, Germany (2006)Google Scholar
  13. 13.
    Falk, J., Keinert, J., Haubelt, C., Teich, J., Bhattacharyya, S.: A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications. In: EMSOFT’08: Proceedings of the 8th ACM international conference on Embedded software (2008)Google Scholar
  14. 14.
  15. 15.
    Gamatié, A., Beux, S.L., Éric Piel, Etien, A., Ben-Atitallah, R.,Marquet, P., Dekeyser, J.L.: A model driven design framework for high performance embedded systems. Tech. Rep. 6614, Institut National de Recherche en Informatique et en Automatique (2008)Google Scholar
  16. 16.
    Gamatié, A., Rutten, E., Yu, H., Boulet, P., Dekeyser, J.L.: Synchronous modeling and analysis of data intensive applications. EURASIP Journal on Embedded Systems 2008(561863), 1–22 (2008).CrossRefGoogle Scholar
  17. 17.
    Girault, A., Lee, B., Lee, E.: Hierarchical finite state machines with multiple concurrency models. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 18(6), 742–760 (1999)CrossRefGoogle Scholar
  18. 18.
    Hsu, C., Bhattacharyya, S.S.: Cycle-Breaking Techniques for Scheduling Synchronous Dataflow Graphs. Tech. Rep. UMIACS-TR-2007-12, Institute for Advanced Computer Studies, University of Maryland at College Park (2007).Google Scholar
  19. 19.
    Janneck, J.W., Miller, I.D., Parlour, D.B., Roquier, G., Wipliez, M., Raulet, M.: Automatic software synthesis of dataflow program: An mpeg-4 simple profile decoder case study. In: Proc. of the IEEE Workshop on Signal Processing Systems (SiPS’08), pp. 281–286 (2008).Google Scholar
  20. 20.
    Janneck, J.W., Miller, I.D., Parlour, D.B., Roquier, G.,Wipliez, M., Raulet, M.: Synthesizing hardware from dataflow programs: An mpeg-4 simple profile decoder case study. In: Proc. Of the IEEE Workshop on Signal Processing Systems (SiPS’08), pp. 287–292 (2008).Google Scholar
  21. 21.
    Kahn, G.: The semantics of simple language for parallel programming. In: IFIP Congress, pp. 471–475 (1974)Google Scholar
  22. 22.
    Keinert, J., Dutta, H., Hannig, F., Haubelt, C., Teich, J.: Model-based synthesis and optimization of static multi-rate image processing algorithms. In: Proceedings of Design, Automation & Test in Europe, pp. 135–140 (2009)Google Scholar
  23. 23.
    Keinert, J., Falk, J., Haubelt, C., Teich, J.: Actor-oriented modeling and simulation of sliding window image processing algorithms. In: Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113–118 (2007)Google Scholar
  24. 24.
    Keinert, J., Haubelt, C., Teich, J.: Modeling and analysis of windowed synchronous algorithms. ICASSP 2006 III, 892–895 (2006)Google Scholar
  25. 25.
    Keinert, J., Haubelt, C., Teich, J.: Automatic synthesis of design alternatives for fast streambased out-of-order communication. In: Proceedings of the 2008 IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration (VLSI-SoC), pp. 265–270. Rhodes Island, Greece (2008)Google Scholar
  26. 26.
    Keinert, J., Streubühr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., Teich, J., Meredith, M.: SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications. Transactions on Design Automation of Electronic Systems 14(1), 1–23 (2009)CrossRefGoogle Scholar
  27. 27.
    Labbani, O.: Modélisation à haut niveau du contrôle dans des applications de traitement systématique à parallélisme massif. Ph.D. thesis, Université des Sciences et Technologies de Lille Laboratoire d’Informatique Fondamentale de Lille, 59655 Villeneuve (2006)Google Scholar
  28. 28.
    Labbani, O., Dekeyser, J.L., Boulet, P., Rutten, E.: Introduction of control into the Gaspard application UML metamodel: Synchronous approach. Tech. Rep. 5794, Laboratoire d’Informatique Fondamentale de Lille, Université des Sciences et Technologies de Lille 59655 Villeneuve d’Ascq Cedex, France (2005)Google Scholar
  29. 29.
    Lee, E.A.: A denotational semantics for dataflow with firing. Tech. rep., EECS, University of California, Berkeley, CA, USA 94720 (1997)Google Scholar
  30. 30.
    Lee, E.A.: Overview of the ptolemy project, technical memorandum no. ucb/erl m03/25. Tech. rep., Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 94720, USA (2004)Google Scholar
  31. 31.
    Lee, E.A., Messerschmitt, D.G.: Synchronous Data Flow. Proceedings of the IEEE 75(9), 1235–1245 (1987)CrossRefGoogle Scholar
  32. 32.
    Lukasiewycz, M., Glaß, M., Haubelt, C., Teich, J., Regler, R., Lang, B.: Concurrent topology and routing optimization in automotive network integration. In: Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC’08), pp. 626–629. Anaheim, USA (2008)Google Scholar
  33. 33.
    Murthy, P.K., Lee, E.A.: Multidimensional synchronous dataflow. IEEE Transactions on Signal Processing Vol 50(7), 2064–2079 (2002)CrossRefGoogle Scholar
  34. 34.
    Necula, G.C., McPeak, S., Rahul, S.P., Weimer, W.: Cil: Intermediate language and tools for analysis and transformation of c programs. Lecture Notes in Computer Science 2304, 209–265 (2002).CrossRefGoogle Scholar
  35. 35.
    Sangiovanni-Vincentelli, A., Sgroi, M., Lavagno, L.: Formal models for communicationbased design. In: Proceedings of CONCUR ’00 (2000).Google Scholar
  36. 36.
    Thörnberg, B., Palkovic, M., Hu, Q., Olsson, L., Kjeldsberg, P.G., O’Nils, M., Catthoor, F.: Bit-width constrained memory hierarchy optimization for real-time video systems. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4), 781–800 (2007)CrossRefGoogle Scholar
  37. 37.
    XILINX: Embedded SystemTools Reference Manual - Embedded Development Kit EDK 8.1ia (2005).Google Scholar
  38. 38.
    Zebelein, C., Falk, J., Haubelt, C., Teich, J.: Classification of General Data Flow Actors into Known Models of Computation. In: Proc. 6th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), pp. 119–128. Anaheim, CA, USA (2008)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Joachim Falk
    • 1
  • Joachim Keinert
    • 2
  • Christian Haubelt
    • 1
  • Jürgen Teich
    • 1
  • Christian Zebelein
    • 1
  1. 1.Hardware-Software-Co-DesignUniversity of Erlangen-NurembergErlangenGermany
  2. 2.Fraunhofer Institute for Integrated Circuits IISErlangenGermany

Personalised recommendations