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Phase-Locked Loop (PLL)

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Abstract

PLL is the heart of practically all electronic components and or modules where different clock frequencies are required to synchronize the data transmitting and receiving to and from externals respectively. The input clock to the PLL is much lower than the DSP maximum clock frequency. PLL is typically being used as a frequency synthesizer to generate the clock for the DSP core. For example, the input clock to the 1.2GHz DSP [1] is 66MHz.

Keywords

Frequency Synthesizer Reference Clock Input Clock Power Supply Rejection Ratio Power Supply Noise 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Texas Instruments Inc (2008) SM320C6455-EP Fixed-Point Digital Signal Processor. SPRS462B. http://focus.ti.com/lit/ds/symlink/sm320c6455-ep.pdf.
  2. 2.
    Cypress Semiconductor Corporation (1997) Jitter in PLL-Based Systems: Causes, Effects and Solutions.Google Scholar
  3. 3.
    Wavecrest (2002) Examining Clock Signals And Measuring Jitter with the WAVECREST SIA-300. Application Note No. 142.Google Scholar
  4. 4.
    Agilent Technologies (2003) Jitter Generation and Jitter Measurements with the Agilent 81134A Pulse Pattern Generator & 54855A Infiniium Oscilloscope.Google Scholar
  5. 5.
    Lin J, Haroun B, Foo T, Wang J, Helmick B, Mayhugh T, Barr C, Kirkpatrick J (2004) A PVT Tolerant 0.18MHz to 600MHz Self-Calibrated Digital PLL in 90nm CMOS Process. ISSCC.Google Scholar

Copyright information

© Springer US 2010

Authors and Affiliations

  1. 1.Texas Instruments IncorporatedStaffordUSA

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