Statistical Evaluation of Fault Tolerance Using Probability Density Functions

  • Miloš Stanisavljević
  • Alexandre Schmid
  • Yusuf Leblebici


The precise evaluation of the reliability of logic circuits has a significant importance in highly defective and future nanotechnologies. It allows verifying the theoretical results on the one side and also enables design improvement with respect to their reliability figure by selecting the most suitable (nano)architecture that satisfies all delay, power, area, and reliability requirements on the other.


Probability Density Function Input Vector Fault Tolerance NAND Gate Redundant Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 13.
    J. von Neumann, Automata Studies. Princeton, NJ: Princeton University Press, 1956, ch. Probabilistic logic and the synthesis of reliable organisms from unreliable components, pp. 43–98.Google Scholar
  2. 123.
    A. S. Sadek, K. Nikolic, and M. Forshaw, “Parallel information and computation with restitution for noise-tolerant nanoscale logic networks,” Nanotechnology, vol. 15, pp. 192–210, 2004.CrossRefGoogle Scholar
  3. 176.
    F. Martorell, A. Rubio, and S. Cotofana, “Analysis of the noise and parameter variations-tolerance of the averaging cell,” in Proceedings of the International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH), 2005, pp. 1–6.Google Scholar
  4. 178.
    F. Martorell and A. Rubio, “Cell architecture for nanoelectronic design,” Microelectronics Journal, vol. 39, no. 8, pp. 1041–1050, 2008.CrossRefGoogle Scholar
  5. 190.
    S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, “Accurate reliability evaluation and enhancement via probabilistic transfer matrices,” in Proceedings of the Design, Automation and Test in Europe (DATE), 2005, pp. 282–287.Google Scholar
  6. 207.
    T. Rejimon and S. Bhanja, “Scalable probabilistic computing models using Bayesian networks,” in Proceedings of the 48th Midwest Symposium on Circuits and Systems (MWSCAS), 7–10 Aug. 2005, pp. 712–715.Google Scholar
  7. 210.
    J. Han, E. Taylor, J. Gao, and J. Fortes, “Faults, error bounds and reliability of nanoelectronic circuits,” in Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP), 23–25 July 2005, pp. 247–253.Google Scholar
  8. 212.
    M. R. Choudhury and K. Mohanram, “Accurate and scalable reliability analysis of logic circuits,” in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 16–20 Apr. 2007, pp. 1–6.Google Scholar
  9. 214.
    D. T. Franco, M. C. Vasconcelosa, L. Navinera, and J.-F. Navinera, “Signal probability for reliability evaluation of logic circuits,” Microelectronics Reliability, vol. 48, no. 8-9, pp. 1586–1591, 2008.CrossRefGoogle Scholar
  10. 215.
    S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, “Estimate of signal probability in combinational logic networks,” in Proceedings of the 1st European Test Conference, 12–14 April 1989, pp. 132–138.Google Scholar
  11. 243.
    R. I. Bahar, J. Mundy, and J. Chen, “A probabilistic-based design methodology for nanoscale computation,” in Proceedings of the International Conference on Computer Aided Design (ICCAD), 9–13 Nov. 2003, pp. 480–486.Google Scholar
  12. 244.
    R. I. Bahar, J. Chen, and J. Mundy, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation. Norwell, MA: Kluwer Academic Publishers, 2004, ch. A probabilistic-based design for nanoscale computation, pp. 133–156.Google Scholar
  13. 245.
    F. Martorell and A. Rubio, “Defect and fault tolerant cell architecture for feasible nanoelectronic designs,” in Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS), 5–7 Sept. 2006, pp. 244–249.Google Scholar
  14. 246.
    A. Papoulis and S. U. Pillai, Probability, Random Variables and Stochastic Processes, 4th ed., New York, NY: McGraw-Hill, 2002.Google Scholar
  15. 247.
    S. Mitra, N. R. Saxena, and E. J. McCluskey, “Common-mode failures in redundant VLSI systems: A survey,” IEEE Transactions on Reliability, vol. 49, no. 3, pp. 285–295, Sept. 2000.CrossRefGoogle Scholar
  16. 248.
    M. R. Choudhury and K. Mohanram, “Reliability analysis of logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 392–405, Mar. 2009.CrossRefGoogle Scholar
  17. 249.
    M. C. Hansen, H. Yalcin, and J. P. Hayes, “Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering,” IEEE Design & Test of Computers, vol. 16, no. 3, pp. 72–80, July–Sept. 1999.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Miloš Stanisavljević
    • 1
  • Alexandre Schmid
    • 1
  • Yusuf Leblebici
    • 1
  1. 1.Ecole Polytechnique Fédérale de LausanneLausanneSwitzerland

Personalised recommendations