Statistical Evaluation of Fault Tolerance Using Probability Density Functions
The precise evaluation of the reliability of logic circuits has a significant importance in highly defective and future nanotechnologies. It allows verifying the theoretical results on the one side and also enables design improvement with respect to their reliability figure by selecting the most suitable (nano)architecture that satisfies all delay, power, area, and reliability requirements on the other.
KeywordsProbability Density Function Input Vector Fault Tolerance NAND Gate Redundant Unit
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