Averaging Design Implementations

  • Miloš Stanisavljević
  • Alexandre Schmid
  • Yusuf Leblebici


The fundamental element enabling reliability improvement in most of the static redundancy techniques is the decision gate, as presented in Chapter 4. One of the fundamental properties of averaging lies in the fact that it reduces the spread of output values caused by different stochastic processes, which are inherently present in hardware designs. In addition, adaptable and reconfigurable designs provide better response in situations outside of the scope or regular operation. Combining the averaging and adaptability principles into a logic circuit design can therefore significantly improve reliability.


Full Adder Fourth Layer Device Failure Redundancy Factor Average Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 7.
    K. K. Likharev, “Single-electron devices and their applications,” Proceedings of the IEEE, vol. 87, no. 4, pp. 606–632, April 1999.CrossRefGoogle Scholar
  2. 13.
    J. von Neumann, Automata Studies. Princeton, NJ: Princeton University Press, 1956, ch. Probabilistic logic and the synthesis of reliable organisms from unreliable components, pp. 43–98.Google Scholar
  3. 15.
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu, “Nano, quantum, and molecular computing: Are we ready for the validation and test challenges?” in Proceedings of the 8th IEEE International High-Level Design Validation and Test Workshop, 2003, pp. 3–7.Google Scholar
  4. 17.
    M. L. Bushnel and W. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. Boston, MA: Springer, 2005.Google Scholar
  5. 26.
    T. Lehtonen, J. Plosila, and J. Isoaho, “On fault tolerance techniques towards nanoscale circuits and systems,” Turku Center for CS, University of Turku, Turku, Finland, Technical Report 708, 2005.Google Scholar
  6. 45.
    C. P. Heij, P. Hadley, and J. E. Mooij, “Single-electron inverter,” Applied Physics Letters, vol. 78, pp. 1140–1142, 2001.CrossRefGoogle Scholar
  7. 48.
    K. Uchida, J. Koga, R. Ohba, and A. Toriumi, “Programmable single-electron transistor logic for future low-power intelligent LSI: Proposal and room-temperature operation,” IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1623–1630, July 2003.CrossRefGoogle Scholar
  8. 51.
    Y. Takahashi, A. Fujiwara, Y. Ono, and K. Murase, “Silicon single-electron devices and their applications,” in Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL), 23–25 May 2000, pp. 411–420.Google Scholar
  9. 55.
    J. Han and P. Jonker, “A system architecture solution for unreliable nanoelectronic devices,” IEEE Transactions on Nanotechnology, vol. 1, no. 4, pp. 201–208, Dec. 2002.CrossRefGoogle Scholar
  10. 111.
    P. G. Depledge, “Fault-tolerant computer systems,” IEE Proceedings A Physical Science, Measurement and Instrumentation, Management and Education, Reviews, vol. 128, no. 4, pp. 257–272, May 1981.CrossRefGoogle Scholar
  11. 132.
    G. Latif-Shabgahi and A. J. Hirst, “A fuzzy voting scheme for hardware and software fault tolerant systems,” Fuzzy Sets and Systems, vol. 150, no. 3, pp. 579–598, 2005.MATHCrossRefMathSciNetGoogle Scholar
  12. 135.
    A. Schmid and Y. Leblebici, “Regular array of nanometer-scale devices performing logic operations with fault-tolerance capability,” in Proceedings of the 4th IEEE Conference on Nanotechnology (IEEE-NANO), 16–19 Aug. 2004, pp. 399–401.Google Scholar
  13. 136.
    A. Schmid and Y. Leblebici, “Realisation of multiple-valued functions using the capacitive threshold logic gate,” IEE Proceedings -Computers and Digital Techniques, vol. 151, no. 6, pp. 435–447, 18 Nov. 2004.CrossRefGoogle Scholar
  14. 137.
    A. Schmid and Y. Leblebici, “A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies,” in Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 10–13 Oct. 2004, pp. 39–47.Google Scholar
  15. 138.
    E. Schuler and L. Carro, “Reliable digital circuits design using analog components,” in Proceedings of the 11th Annual IEEE International Mixed-Signals Testing Workshop (IMSTW), Cannes, France, June 2005, pp. 166–170.Google Scholar
  16. 139.
    A. Michels, L. Petroli, C. A. L. Lisboa, F. Kastensmidt, and L. Carro, “SET fault tolerant combinational circuits based on majority logic,” in Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 4–6 Oct. 2006, pp. 345–352.Google Scholar
  17. 140.
    S. Aunet and V. Beiu, “Ultra low power fault tolerant neural inspired CMOS logic,” in Proceedings of the IEEE International Joint Conference on Neural Networks (IJCNN), vol. 5, 31 July–4 Aug. 2005, pp. 2843–2848.Google Scholar
  18. 141.
    S. Aunet, B. Oelmann, P. A. Norseng, and Y. Berg, “Real-time reconfigurable subthreshold CMOS perceptron,” IEEE Transactions on Neural Networks, vol. 19, no. 4, pp. 645–657, April 2008.CrossRefGoogle Scholar
  19. 218.
    D. Bradley, C. Ortega-Sanchez, and A. Tyrrell, “Embryonics+immunotronics: A bio-inspired approach to fault tolerance,” in Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, 13–15 July 2000, pp. 215–223.Google Scholar
  20. 219.
    S. Aunet, B. Oelmann, S. Abdalla, and Y. Berg, “Reconfigurable subthreshold CMOS perceptron,” in Proceedings of the IEEE International Joint Conference on Neural Networks (IJCNN), vol. 3, 25–29 July 2004, pp. 1983–1988.Google Scholar
  21. 220.
    S. Haykin, Neural Networks: A Comprehensive Foundation. Upper Saddle River, NJ: Prentice Hall, Inc., 1999.Google Scholar
  22. 221.
    K. Yamamori, S. Horiguchi, J. H. Kim, S. K. Park, and B. H. Ham, “The efficient design of fault-tolerant artificial neural networks,” in Proceedings of the IEEE International Conference on Neural Networks, vol. 3, 27 Nov.–1 Dec. 1995, pp. 1487–1491.Google Scholar
  23. 222.
    P. Kerlirzin and P. Refregier, “Theoretical investigation of the robustness of multilayer perceptrons: Analysis of the linear case and extension to nonlinear networks,” IEEE Transactions on Neural Networks, vol. 6, no. 3, pp. 560–571, May 1995.CrossRefGoogle Scholar
  24. 223.
    R. C. Frye, E. A. Rietman, and C. C. Wong, “Back-propagation learning and nonidealities in analog neural network hardware,” IEEE Transactions on Neural Networks, vol. 2, no. 1, pp. 110–117, Jan. 1991.CrossRefGoogle Scholar
  25. 225.
    M. J. S. Smith, “An analog integrated neural network capable of learning the Feigenbaum logistic map,” IEEE Transactions on Circuits and Systems, vol. 37, no. 6, pp. 841–844, June 1990.CrossRefGoogle Scholar
  26. 226.
    A. Schmid and Y. Leblebici, “Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors,” in Proceedings of the 3rd IEEE Conference on Nanotechnology (IEEE-NANO), vol. 2, 12–14 Aug. 2003, pp. 516–519.Google Scholar
  27. 227.
    M. Stanisavljević, A. Schmid, and Y. Leblebici, “Analysis of reliability in nanoscale circuits and systems based on a-priori statistical fault-modeling methodology,” in Proceedings of the 48th Midwest Symposium on Circuits and Systems (MWSCAS), 7–10 Aug. 2005, pp. 1565–1568.Google Scholar
  28. 228.
    S. Aunet and M. Hartman, “Real-time reconfigurable threshold elements and some applications to neural hardware,” in Proceedings of the International Conference Evolvable System (ICES), Trondheim, Norway, Mar. 2003, pp. 365–376.Google Scholar
  29. 229.
    V. Beiu, S. Aunet, R. R. Rydberg III, A. Djupdal, and J. Nyathi, “The vanishing majority gate trading power and speed for reliability,” in Proceedings of the International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH), 2005, pp. 1–8.Google Scholar
  30. 230.
    D. E. Rumelhart, G. E. Hinton, and R. J. Williams, Parallel Distributed Processing: Explorations in the Microstructure of Cognition. Volume 1: Foundations. Cambridge, MA: MIT Press, 1986, ch. Learning internal representations by error propagation, pp. 318–362.Google Scholar
  31. 231.
    G. Cauwenberghs, “Analog VLSI stochastic perturbative learning architectures,” Analog Integrated Circuits and Signal Processing, vol. 13, no. 1–2, pp. 195–209, 1997.CrossRefGoogle Scholar
  32. 232.
    A. Schmid and Y. Leblebici, “Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1156–1166, Nov. 2004.CrossRefGoogle Scholar
  33. 233.
    M. Stanisavljević, A. Schmid, and Y. Leblebici, “Fault-tolerance of robust feed-forward architecture using single-ended and differential deep-submicron circuits under massive defect density,” in Proceedings of the International Joint Conference on Neural Networks (IJCNN), 16–21 July 2006, pp. 2771–2778.Google Scholar
  34. 234.
    L. Heller, W. Griffin, J. Davis, and N. Thoma, “Cascode voltage switch logic: A differential CMOS logic family,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). Digest of Technical Papers, vol. XXVII, Feb. 1984, pp. 16–17.Google Scholar
  35. 235.
    A. M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee, and J. Gautier, “Few electron devices: towards hybrid CMOS-SET integrated circuits,” in Proceedings of the 39th Design Automation Conference (DAC), 10–14 June 2002, pp. 88–93.Google Scholar
  36. 237.
    J. R. Tucker, “Complementary digital logic based on the “Coulomb blockade,” Journal of Applied Physics, vol. 72, no. 9, pp. 4399–4413, 1992.CrossRefGoogle Scholar
  37. 238.
    M. M. Ziegler and M. R. Stan, “CMOS/nano co-design for crossbar-based molecular electronic systems,” IEEE Transactions on Nanotechnology, vol. 2, no. 4, pp. 217–230, Dec. 2003.CrossRefGoogle Scholar
  38. 239.
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, and A. M. Ionescu, “SETMOS: A novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM). Technical Digest, 8–10 Dec. 2003, pp. 29.7.1–29.7.4.Google Scholar
  39. 240.
    H. Iwamura, M. Akazawa, and Y. Amemiya, “Single-electron majority logic circuits,” IEICE Transactions on Electronics, vol. E81-C, pp. 42–48, 1998.Google Scholar
  40. 241.
    M. Sulieman and V. Beiu, “Design and analysis of SET circuits: using MATLAB modules and SIMON,” in Proceedings of the 4th IEEE Conference on Nanotechnology (IEEE-NANO), 16–19 Aug. 2004, pp. 618–621.Google Scholar
  41. 242.
    C. Wasshuber, H. Kosina, and S. Selberherr, “SIMON-a simulator for single-electron tunnel devices and circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 937–944, Sept. 1997.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Miloš Stanisavljević
    • 1
  • Alexandre Schmid
    • 1
  • Yusuf Leblebici
    • 1
  1. 1.Ecole Polytechnique Fédérale de LausanneLausanneSwitzerland

Personalised recommendations