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Reliability Evaluation Techniques

  • Miloš Stanisavljević
  • Alexandre Schmid
  • Yusuf Leblebici
Chapter

Abstract

The expectations are that the future nanocircuits will exhibit higher frequency of failures. The higher density of transistors on-chip is one of the reasons for this behavior. In particular, as feature sizes are aggressively scaled, the processing of ICs becomes more complex and inevitably introduces more defects. Other factors such as geometric variations, or related to the tiny amounts of energy which are required to enable the switching of nanodevices, make them susceptible to transient failures and negatively impact on reliability. Architectures built from emerging nanodevices will be extremely susceptible to parameter variations, fabrication defects, and transient failures induced by environmental/external causes [2, 164].

Keywords

Monte Carlo Bayesian Network Reliability Evaluation NAND Gate Fault Tree Analysis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Miloš Stanisavljević
    • 1
  • Alexandre Schmid
    • 1
  • Yusuf Leblebici
    • 1
  1. 1.Ecole Polytechnique Fédérale de LausanneLausanneSwitzerland

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