Skip to main content
SpringerLink
Log in
Book cover

Reliability of Nanoscale Circuits and Systems pp 35–47Cite as

Fault-Tolerant Architectures and Approaches

  • Chapter
  • First Online:

Abstract

Ever since humans first fashioned tools, they have had to ponder on their reliability and cope with the consequences of their failure. The unprecedented complexity of electronic appliances in the digital age has fostered the study and practice of fault tolerance, with the objective of delivering acceptable performance, even during sub-optimal or adverse circumstances. Over the past 50 years, fault tolerance has steadily advanced in stride with the permeation of computers into all aspects of society and human welfare [42].

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, “A defect-tolerant computer architecture: Opportunities for nanotechnology,” Science, vol. 280, pp. 1716–1721, 1998.

    Article  Google Scholar 

  2. K. Nikolic, A. Sadek, and M. Forshaw, “Fault-tolerant techniques for nanocomputers,” Nanotechnology, vol. 13, pp. 357–362, 2002.

    Article  Google Scholar 

  3. J. von Neumann, Automata Studies. Princeton, NJ: Princeton University Press, 1956, ch. Probabilistic logic and the synthesis of reliable organisms from unreliable components, pp. 43–98.

    Google Scholar 

  4. T. Lehtonen, J. Plosila, and J. Isoaho, “On fault tolerance techniques towards nanoscale circuits and systems,” Turku Center for CS, University of Turku, Turku, Finland, Technical Report 708, 2005.

    Google Scholar 

  5. V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, “A fresh look at majority multiplexing when devices get into the picture,” in Proceedings of the 7th IEEE Conference on Nanotechnology (IEEE-NANO), 2–5 Aug. 2007, pp. 883–888.

    Google Scholar 

  6. V. Beiu, “Grand challenges of nanoelectronics and possible architectural solutions: What do Shannon, von Neumann, Kolmogorov, and Feynman have to do with Moore,” in Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL), 13–16 May 2007, p. 1–6.

    Google Scholar 

  7. J. Han and P. Jonker, “A system architecture solution for unreliable nanoelectronic devices,” IEEE Transactions on Nanotechnology, vol. 1, no. 4, pp. 201–208, Dec. 2002.

    Article  Google Scholar 

  8. D. P. Siewiorek and R. S. Swarz, The Theory and Practice of Reliable System Design. Bedford, MA: Digital Press, 1982.

    Google Scholar 

  9. P. G. Depledge, “Fault-tolerant computer systems,” IEE Proceedings A Physical Science, Measurement and Instrumentation, Management and Education, Reviews, vol. 128, no. 4, pp. 257–272, May 1981.

    Article  Google Scholar 

  10. J. A. Abraham and D. P. Siewiorek, “An algorithm for the accurate reliability evaluation of triple modular redundancy networks,” IEEE Transactions on Computers, vol. 1, no. 7, pp. 682–692, July 1974.

    Article  Google Scholar 

  11. B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems. Reading, MA: Addison-Wesley Publishing Company, 1989.

    Google Scholar 

  12. S. Spagocci and T. Fountain, “Fault rates in nanochip devices,” Proceedings of the Electrochemical Society, vol. 98, no. 19, 1999, pp. 582–593.

    Google Scholar 

  13. M. Stanisavljević, A. Schmid, and Y. Leblebici, “Optimization of nanoelectronic systems’ reliability under massive defect density using cascaded R-fold modular redundancy,” Nanotechnology, vol. 19, no. 46, pp. 1–9, 2008.

    Google Scholar 

  14. R. I. Bahar, J. Chen, and J. Mundy, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation. Norwell, MA: Kluwer Academic Publishers, 2004, ch. Nanocomputing in the presence of defects and faults: A survey, pp. 39–72.

    Google Scholar 

  15. W. H. Pierce, Failure-Tolerant Computer Design. New York, NY: Academic Press, 1965.

    Google Scholar 

  16. J. Han and P. Jonker, “From massively parallel image processors to fault-tolerant nanocomputers,” in Proceedings of the 17th International Conference on Pattern Recognition (ICPR), vol. 3, 23–26 Aug. 2004, pp. 2–7.

    Google Scholar 

  17. J. Han, J. Gao, P. Jonker, Y. Qi, and J. A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics,” IEEE Design & Test of Computers, vol. 22, no. 4, pp. 328–339, July–Aug. 2005.

    Article  Google Scholar 

  18. J. Tryon, Redundancy Techniques for Computing Systems. Washington, DC: Spartan Books, 1962, ch. Quadded logic, pp. 205–228.

    Google Scholar 

  19. S. Roy and V. Beiu, “Multiplexing schemes for cost-effective fault-tolerance,” in Proceedings of the 4th IEEE Conference on Nanotechnology (IEEE-NANO), 16–19 Aug. 2004, pp. 589–592.

    Google Scholar 

  20. S. Roy and V. Beiu, “Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures,” IEEE Transactions on Nanotechnology, vol. 4, no. 4, pp. 441–451, July 2005.

    Article  Google Scholar 

  21. A. S. Sadek, K. Nikolic, and M. Forshaw, “Parallel information and computation with restitution for noise-tolerant nanoscale logic networks,” Nanotechnology, vol. 15, pp. 192–210, 2004.

    Article  Google Scholar 

  22. J. Han and P. Jonker, “A defect- and fault-tolerant architecture for nanocomputers,” Nanotechnology, vol. 14, pp. 224–230, 2003.

    Article  Google Scholar 

  23. G. Roelke, R. Baldwin, and D. Bulutoglu, “Analytical models for the performance of von Neumann multiplexing,” IEEE Transactions on Nanotechnology, vol. 6, no. 1, pp. 75–89, Jan. 2007.

    Article  Google Scholar 

  24. M. Forshaw, K. Nikolic, and A. S. Sadek, “ANSWERS: Autonomous nanoelectronic systems with extended replication and signaling,” Microelectronics Advance Research Initiative (MEL-ARI), Technical Report 28667, 2001, 3rd Year Annual Report.

    Google Scholar 

  25. M. Stanisavljević, A. Schmid, and Y. Leblebici, “Optimization of the averaging reliability technique using low redundancy factors for nanoscale technologies,” IEEE Transactions on Nanotechnology, vol. 8, no. 3, pp. 379–390, 2009.

    Article  Google Scholar 

  26. M. K. Stojcev, G. L. Djordjevic, and M. D. Krstic, “A hardware mid-value select voter architecture,” Microelectronics Journal, vol. 32, no. 1, pp. 149–162, 2001.

    Article  Google Scholar 

  27. M. D. Krstic, M. K. Stojcev, G. L. Djordjevic, and I. D. Andrejic, “A mid-value select voter,” Microelectronics and Reliability, vol. 45, no. 3-4, pp. 733–738, 2005.

    Article  Google Scholar 

  28. G. Latif-Shabgahi, J. M. Bass, and S. Bennett, “Efficient implementation of inexact majority and median voters,” Electronics Letters, vol. 36, no. 15, pp. 1326–1328, 2000.

    Article  Google Scholar 

  29. G. Latif-Shabgahi and A. J. Hirst, “A fuzzy voting scheme for hardware and software fault tolerant systems,” Fuzzy Sets and Systems, vol. 150, no. 3, pp. 579–598, 2005.

    Article  MATH  MathSciNet  Google Scholar 

  30. C. Chiou and T. C. Yang, “Self-purging redundancy with adjustable threshold for tolerating multiple module failures,” Electronics Letters, vol. 31, no. 11, pp. 930–931, 1995.

    Article  Google Scholar 

  31. G. Latif-Shabgahi, J. M. Bass, and S. Bennett, “History-based weighted average voter: a novel software voting algorithm for fault-tolerant computer systems,” in Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing, 7–9 Feb. 2001, pp. 402–409.

    Google Scholar 

  32. A. Schmid and Y. Leblebici, “Regular array of nanometer-scale devices performing logic operations with fault-tolerance capability,” in Proceedings of the 4th IEEE Conference on Nanotechnology (IEEE-NANO), 16–19 Aug. 2004, pp. 399–401.

    Google Scholar 

  33. A. Schmid and Y. Leblebici, “Realisation of multiple-valued functions using the capacitive threshold logic gate,” IEE Proceedings -Computers and Digital Techniques, vol. 151, no. 6, pp. 435–447, 18 Nov. 2004.

    Article  Google Scholar 

  34. A. Schmid and Y. Leblebici, “A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies,” in Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 10–13 Oct. 2004, pp. 39–47.

    Google Scholar 

  35. E. Schuler and L. Carro, “Reliable digital circuits design using analog components,” in Proceedings of the 11th Annual IEEE International Mixed-Signals Testing Workshop (IMSTW), Cannes, France, June 2005, pp. 166–170.

    Google Scholar 

  36. A. Michels, L. Petroli, C. A. L. Lisboa, F. Kastensmidt, and L. Carro, “SET fault tolerant combinational circuits based on majority logic,” in Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 4–6 Oct. 2006, pp. 345–352.

    Google Scholar 

  37. S. Aunet and V. Beiu, “Ultra low power fault tolerant neural inspired CMOS logic,” in Proceedings of the IEEE International Joint Conference on Neural Networks (IJCNN), vol. 5, 31 July–4 Aug. 2005, pp. 2843–2848.

    Google Scholar 

  38. S. Aunet, B. Oelmann, P. A. Norseng, and Y. Berg, “Real-time reconfigurable subthreshold CMOS perceptron,” IEEE Transactions on Neural Networks, vol. 19, no. 4, pp. 645–657, April 2008.

    Article  Google Scholar 

  39. S. Mitra, M. Zhang, N. Seifert, T. M. Mak, and K. S. Kim, “Soft error resilient system design through error correction,” in Proceedings of the IFIP International Conference on Very Large Scale Integration, 16–18 Oct. 2006, pp. 332–337.

    Google Scholar 

  40. Y. M. Hsu and J. Swartzlander, E. E., “VLSI concurrent error correcting adders and multipliers,” in Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT), 27–29 Oct. 1993, pp. 287–294.

    Google Scholar 

  41. S. A. Al-Arian and M. B. Gumusel, “HPTR: Hardware partition in time redundancy technique for fault tolerance,” in Proceedings of the IEEE SoutheastCon, 12–15 April 1992, pp. 630–633.

    Google Scholar 

  42. H. Al-Asaad and E. Czeck, “Concurrent error correction in iterative circuits by recomputing with partitioning and voting,” in Proceedings of the 11th Annual IEEE VLSI Test Symposium. Digest of Papers, 6–8 April 1993, pp. 174–177.

    Google Scholar 

  43. W. L. Gallagher and J. Swartzlander, E. E., “Fault-tolerant Newton-Raphson and Goldschmidt dividers using time shared TMR,” IEEE Transactions on Computers, vol. 49, no. 6, pp. 588–595, June 2000.

    Google Scholar 

  44. W. J. Townsend, J. A. Abraham, and J. Swartzlander, E. E., “Quadruple time redundancy adders [error correcting adder],” in Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 3–5 Nov. 2003, pp. 250–256.

    Google Scholar 

  45. A. J. KleinOsowski and D. J. Lilja, “The NanoBox project: Exploring fabrics of self-correcting logic blocks for high defect rate molecular device technologies,” in Proceedings of the IEEE Computer society Annual Symposium on VLSI, 19–20 Feb. 2004, pp. 19–24.

    Google Scholar 

  46. M. Zhang and N. R. Shanbhag, “A CMOS design style for logic circuit hardening,” in Proceedings of the 43rd IEEE International Annual Reliability Physics Symposium, 17–21 Apr. 2005, pp. 223–229.

    Google Scholar 

  47. M. R. Choudhury, Q. Zhou, and K. Mohanram, “Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 5–9 Nov. 2006, pp. 204–209.

    Google Scholar 

  48. K. Mohanram and N. A. Touba, “Partial error masking to reduce soft error failure rate in logic circuits,” in Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 3–5 Nov. 2003, pp. 433–440.

    Google Scholar 

  49. K. Mohanram, “Error detection and tolerance for scaled electronic technologies,” in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT), 1–3 Oct. 2008, pp. 83–83.

    Google Scholar 

  50. M. R. Choudhury and K. Mohanram, “Approximate logic circuits for low overhead, non-intrusive concurrent error detection,” in Proceedings of the Design, Automation and Test in Europe (DATE), 10–14 Mar. 2008, pp. 903–908.

    Google Scholar 

  51. D. Clark, “Teramac: Pointing the way to real-world nanotechnology,” IEEE Computational Science & Engineering, vol. 5, no. 3, pp. 88–90, 1998.

    Article  Google Scholar 

  52. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, “Low overhead fault-tolerant FPGA systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 2, pp. 212–221, June 1998.

    Article  Google Scholar 

  53. D. Mange, M. Sipper, A. Stauffer, and G. Tempesti, “Toward robust integrated circuits: The embryonics approach,” Proceedings of the IEEE, vol. 88, no. 4, pp. 516–543, April 2000.

    Article  Google Scholar 

  54. M. Mishra and S. C. Goldstein, “Defect tolerance at the end of the roadmap,” in Proc. International Test Conference (ITC), vol. 1, Sept. 30–Oct. 2, 2003, pp. 1201–1210.

    Google Scholar 

  55. S. C. Goldstein, “The impact of the nanoscale on computing systems,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 6–10 Nov. 2005, pp. 655–661.

    Google Scholar 

  56. G. Snider, P. Kueckes, and R. Williams, “CMOS-like logic in defective, nanoscale crossbars,” Nanotechnology, vol. 15, pp. 881–891, 2004.

    Article  Google Scholar 

  57. D. Bhaduri, S. Shukla, P. Graham, and M. Gokhale, “Comparing reliability-redundancy tradeoffs for two von Neumann multiplexing architectures,” IEEE Transactions on Nanotechnology, vol. 6, no. 3, pp. 265–279, May 2007.

    Article  Google Scholar 

  58. R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu, and M. Pedram, “Architectures for silicon nanoelectronics and beyond,” Computers, vol. 40, no. 1, pp. 25–33, 2007.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Ecole Polytechnique Fédérale de Lausanne, 1015, Lausanne, Switzerland

    Miloš Stanisavljević, Alexandre Schmid & Yusuf Leblebici

Authors
  1. Miloš Stanisavljević
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alexandre Schmid
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yusuf Leblebici
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Miloš Stanisavljević .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Stanisavljević, M., Schmid, A., Leblebici, Y. (2011). Fault-Tolerant Architectures and Approaches. In: Reliability of Nanoscale Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6217-1_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6217-1_4

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-6216-4

  • Online ISBN: 978-1-4419-6217-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation