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System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

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Integrated Optical Interconnect Architectures for Embedded Systems

Part of the book series: Embedded Systems ((EMSY))

Abstract

Design trends for next-generation multi-processor systems on chip (MPSoC) point to the integration of a large number of processing elements onto a single chip, requiring high-performance interconnect structures for high-throughput communication. On-chip optical interconnect and 3D die stacking are currently considered to be the two most promising paradigms in this design context. New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design. We investigate design tradeoffs for 3D MPSoC integrating optical networks-on-chip (ONoC) and highlight current and short-term design trends. We also propose a system-level design space exploration flow that takes routing capabilities of optical interconnect into account. The resulting application-to-architecture mappings demonstrate the benefits of the presented 3D MPSoC architectures and the efficiency of our system-level exploration flow.

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Authors and Affiliations

  1. École Polytechnique de Montréal, Montreal, QC, Canada

    Sébastien Le Beux, Jelena Trajkovic, Gabriela Nicolescu & Guy Bois

  2. Ecole Centrale de Lyon – Lyon Institute of Nanotechnology, University of Lyon, 36 avenue Guy de Collongue, Ecully Cedex, 69134, France

    Sébastien Le Beux & Ian O’Connor

  3. STMicroelectronics (Canada) Inc., Ottawa, ON, Canada

    Pierre Paulin

Authors
  1. Sébastien Le Beux
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  2. Jelena Trajkovic
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  3. Ian O’Connor
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  4. Gabriela Nicolescu
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  5. Guy Bois
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  6. Pierre Paulin
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Correspondence to Sébastien Le Beux .

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Editors and Affiliations

  1. CNRS UMR 5270, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, av. Guy de Collongue 36, Ecully, 69134, France

    Ian O'Connor

  2. Dpt. Génie Informatique & Génie Logiciel, Ecole Polytechnique de Montreal, chemin de Polytechnique 2500, Montreal, H3T 1J4, Québec, Canada

    Gabriela Nicolescu

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Le Beux, S., Trajkovic, J., O’Connor, I., Nicolescu, G., Bois, G., Paulin, P. (2013). System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures. In: O'Connor, I., Nicolescu, G. (eds) Integrated Optical Interconnect Architectures for Embedded Systems. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6193-8_8

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  • DOI: https://doi.org/10.1007/978-1-4419-6193-8_8

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-6192-1

  • Online ISBN: 978-1-4419-6193-8

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