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System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

  • Sébastien Le Beux
  • Jelena Trajkovic
  • Ian O’Connor
  • Gabriela Nicolescu
  • Guy Bois
  • Pierre Paulin
Chapter
Part of the Embedded Systems book series (EMSY)

Abstract

Design trends for next-generation multi-processor systems on chip (MPSoC) point to the integration of a large number of processing elements onto a single chip, requiring high-performance interconnect structures for high-throughput communication. On-chip optical interconnect and 3D die stacking are currently considered to be the two most promising paradigms in this design context. New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design. We investigate design tradeoffs for 3D MPSoC integrating optical networks-on-chip (ONoC) and highlight current and short-term design trends. We also propose a system-level design space exploration flow that takes routing capabilities of optical interconnect into account. The resulting application-to-architecture mappings demonstrate the benefits of the presented 3D MPSoC architectures and the efficiency of our system-level exploration flow.

Keywords

Optical network-on-chip (ONoC) Multi-processor systems on chip (MPSoC) 3D die stacking Design space exploration 

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Sébastien Le Beux
    • 1
    • 2
  • Jelena Trajkovic
    • 1
  • Ian O’Connor
    • 2
  • Gabriela Nicolescu
    • 1
  • Guy Bois
    • 1
  • Pierre Paulin
    • 3
  1. 1.École Polytechnique de MontréalMontrealCanada
  2. 2.Ecole Centrale de Lyon – Lyon Institute of NanotechnologyUniversity of LyonEcully CedexFrance
  3. 3.STMicroelectronics (Canada) Inc.OttawaCanada

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