Reconfigurable Networks-on-Chip

Part of the Embedded Systems book series (EMSY)


There is little doubt that the most important limiting factors of the ­performance of next-generation chip multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic networks-on-chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, novel components such as silicon microrings, photonic switches and other reconfigurable elements can be integrated to route signals in a data-transparent way.

In this chapter, we look at the behavior of on-chip network traffic and show how the locality in space and time which it exhibits can be advantageously exploited by what we will define as “slowly reconfiguring” networks. We will review existing work on photonic reconfigurable NoCs, and provide implementation details and a performance and power characterization of our own reconfigurable photonic NoC proposal in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings.

Key words

Network-on-chip Optical interconnects Reconfigurable networks 



This work was supported by the European Commission’s 6th FP Network of Excellence on Micro-Optics (NEMO), the BELSPO IAP P6/10 photonics@be network sponsored by the Belgian Science Policy Office, the GOA, the FWO, the OZR, the Methusalem and Hercules foundations. The work of C. Debaes is supported by the FWO (Fund for Scientic Research—Flanders) under a research fellowship.


  1. 1.
    Agelis S, Jacobsson S, Jonsson M, Alping A, Ligander P (2002) Modular interconnection system for optical PCB and backplane communication. In: IEEE International parallel & distributed processing symposium, pp 245–250Google Scholar
  2. 2.
    Artundo I, Desmet L, Heirman W, Debaes C, Dambre J, Van Campenhout J, Thienpont H (2006) Selective optical broadcast component for reconfigurable multiprocessor interconnects. IEEE J Sel Top Quantum Electron Special Issue Opt Communication 12(4):828–837. DOI 101109/JSTQE2006876158CrossRefGoogle Scholar
  3. 3.
    Artundo I, Heirman W, Debaes C, Loperena M, Van Campenhout J, Thienpont H (2009) Low-power reconfigurable network architecture for on-chip photonic interconnects. In: 17th IEEE symposium on high performance interconnects, New York, pp 163–169. DOI 101109/HOTI200927Google Scholar
  4. 4.
    Artundo I, Manjarres D, Heirman W, Debaes C, Dambre J, Van Campenhout J, Thienpont H (2006) Reconfigurable interconnects in DSM systems: a focus on context switch behavior. In: Frontiers of high performance computing and networking—ISPA 2006 workshops, vol 4331. Springer, Berlin, pp 311–321Google Scholar
  5. 5.
    Ascia G, Catania V, Palesi M (2004) Multi-objective mapping for mesh-based NoC architectures. In: Proceedings of ISSS-CODES, Stockholm, SwedenGoogle Scholar
  6. 6.
    Assefa S, Xia F, Vlasov YA (2010) Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects. Nature 464:80–84. DOI 101038/ nature08813CrossRefGoogle Scholar
  7. 7.
    Barford P, Crovella M (1998) Generating representative web workloads for network and server performance evaluation. In: Proceedings of the 1998 ACM SIGMETRICS joint international conference on measurement and modeling of computer systems, Madison, pp 151–160. DOI 101145/277851277897Google Scholar
  8. 8.
    Barker KJ, Benner A, Hoare R, Hoisie A, Jones AK, Kerbyson DK, Li D, Melhem R, Rajamony R, Schenfeld E, Shao S, Stunkel C, Walker P (2005) On the feasibility of optical circuit switching for high performance computing systems. In: SC ‘05: proceedings of the 2005 ACM/IEEE conference on supercomputing, IEEE Computer Society, Washington, p 16. DOI 101109/SC200548Google Scholar
  9. 9.
    Barnes TH, Eiju T, Matsuda K, Ichikawa H, Taghizadeh MR, Turunen J (1992) Reconfigurable free-space optical interconnections with a phase-only liquid-crystal spatial light modulator. Appl Opt 31:5527–5535CrossRefGoogle Scholar
  10. 10.
    Beausoleil RG, Ahn J, Binkert N, Davis A, Fattal D, Fiorentino M, Jouppi NP, McLaren M, Santori CM, Schreiber RS, Spillane SM, Vantrease D, Xu Q (2008) A nanophotonic interconnect for high-performance many-core computation. IEEE LEOS Newslett 22(3):15–22Google Scholar
  11. 11.
    Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) QNoC: QoS architecture and design process for network on chip. In: J Syst Arch 50:105–128CrossRefGoogle Scholar
  12. 12.
    Brière M, Girodias B, Bouchebaba Y, Nicolescu G, Mieyeville F, Gaffiot F, O’Connor I (2007) System level assessment of an optical NoC in an MPSoC platform. In: Proceedings of the conference on design, automation and test in Europe, pp 1084–1089Google Scholar
  13. 13.
    Cassinelli A, Takashi K (2002) Presentation of OCULAR-III architecture (using guide-wave interconnection modules). In: OSAKA research meetingGoogle Scholar
  14. 14.
    Christie P, Stroobandt D (2000) The interpretation and application of Rent’s rule. IEEE Trans Very Large Scale Integr Syst 8(6):639–648. DOI 101109/92902258CrossRefGoogle Scholar
  15. 15.
    Dally WJ, Towles B (2002) Route packets, not wires: on-chip interconnection networks. In: Design automation conference, pp 684–689Google Scholar
  16. 16.
    Debaes C, Artundo I, Heirman W, Van Campenhout J, Thienpont H (2010) Cycle-accurate evaluation of reconfigurable photonic networks-on-chip. In: Righini GC (ed) Proceedings of SPIE photonics Europe, vol 7719. SPIE, p 771916. DOI 101117/ 12854744Google Scholar
  17. 17.
    Faruque M, Weiss G, Henkel J (2006) Bounded arbitration algorithm for QoS-supported on-chip communication. In: Proceedings of the 4th international conf hardware/software codesign and system synthesis, pp 142–147Google Scholar
  18. 18.
    Fidaner O, Demir HV, Sabnis VA, Zheng JF, Harris JSJ, Miller DAB (2006) Integrated photonic switches for nanosecond packet-switched optical wavelength conversion. Opt Express 14(1):361 (2006)CrossRefGoogle Scholar
  19. 19.
    Gao Y, Jin Y, Chang Z, Hu W (2009) Ultra-low latency reconfigurable photonic network on chip architecture based on application pattern. In: Proceedings of NFOECGoogle Scholar
  20. 20.
    Geer D (2005) Chip makers turn to multicore processors. IEEE Comput 38(5):11–13 (2005). DOI 101109/MC2005160Google Scholar
  21. 21.
    Gheorghita SV, Palkovic M, Hamers J, Vandecappelle A, Mamagkakis S, Basten T, Eeckhout L, Corporaal H, Catthoor F, Vandeputte F, Bosschere KD (2009) System-scenario-based design of dynamic embedded systems. ACM Trans Des Autom Electron Syst 14(1):1–45 (2009). DOI 101145/14552291455232CrossRefGoogle Scholar
  22. 22.
    Green WMJ, Rooks MJ, Sekaric L, Vlasov YA (2007) Ultra-compact, low RF power, 10  Gb/s silicon Mach–Zehnder modulator. Opt Express 15(25):17106–17113CrossRefGoogle Scholar
  23. 23.
    Greenfield D, Banerjee A, Lee JG, Moore S (2007) Implications of Rent’s rule for NoC design and its fault-tolerance. In: Proceedings of the first international symposium on networks-on-chips (NOCS‘07), Princeton, pp 283–294Google Scholar
  24. 24.
    Greenfield D, Moore S (2008) Fractal communication in software data dependency graphs. In: Proceedings of the 20th ACM symposium on parallelism in algorithms and architectures (SPAA’08), Munich, pp 116–118. DOI 101145/13785331378555Google Scholar
  25. 25.
    Gu H, Xu J, Zhang W (2009) A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip. In: Proceedings of the conference on design automation and test in Europe, Nice, pp 3–8Google Scholar
  26. 26.
    Gupta V, Schenfeld E (1994) Performance analysis of a synchronous, circuit-switched interconnection cached network. In: ICS ’94: proceedings of the 8th international conference on supercomputing, ACM, Manchester, pp 246–255. DOI 101145/ 181181181540Google Scholar
  27. 27.
    Guz Z, Walter I, Bolotin E, Cidon I, Ginosar R, Kolodny A (2006) Efficient link capacity and QOS design for network-on-chip. In: Proceedings of the conference on design, automation and test in Europe, pp 9–14Google Scholar
  28. 28.
    Habata S, Umezawa K, Yokokawa M, Kitawaki S (2004) Hardware system of the earth simulator. Parallel Comput 30(12):1287–1313. DOI 101016/jparco200409004CrossRefGoogle Scholar
  29. 29.
    Han X, Chen RT (2004) Improvement of multiprocessing performance by using optical centralized shared bus. Proc SPIE 5358:80–89CrossRefGoogle Scholar
  30. 30.
    Hawkins C, Small BA, Wills DS, Bergman K (2007) The data vortex, an all optical path multicomputer interconnection network. IEEE Trans Parallel Distr Syst 18(3):409–420. DOI 101109/TPDS200748CrossRefGoogle Scholar
  31. 31.
    Heirman W (2008) Reconfigurable optical interconnection networks for shared-memory multiprocessor architectures. PhD Thesis, Ghent UniversityGoogle Scholar
  32. 32.
    Heirman W, Artundo I, Carvajal D, Desmet L, Dambre J, Debaes C, Thienpont H, Van Campenhout J (2005) Wavelength tuneable reconfigurable optical interconnection network for shared-memory machines. In: Proceedings of the 31st European conference on optical communication (ECOC 2005), vol 3. The Institution of Electrical Engineers, Glasgow, pp 527–528Google Scholar
  33. 33.
    Heirman W, Dambre J, Artundo I, Debaes C, Thienpont H, Stroobandt D, Van Campenhout J (2008) Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems. Photon Netw Commun 15(1):25–40. DOI 101007/s11107-007-0084-zCrossRefGoogle Scholar
  34. 34.
    Heirman W, Dambre J, Stroobandt D, Van Campenhout, J (2008) Rent’s rule and parallel programs: characterizing network traffic behavior. In: Proceedings of the 2008 international workshop on system level interconnect prediction (SLIP’08), ACM, Newcastle, pp 87–94Google Scholar
  35. 35.
    Heirman W, Dambre J, Van Campenhout J (2007) Synthetic traffic generation as a tool for dynamic interconnect evaluation. In: Proceedings of the 2007 international workshop on system level interconnect prediction (SLIP’07), ACM, Austin, pp 65–72Google Scholar
  36. 36.
    Heirman W, Dambre J, Van Campenhout J, Debaes C, Thienpont H (2005) Traffic temporal analysis for reconfigurable interconnects in shared-memory systems. In: Proceedings of the 19th IEEE international parallel & distributed processing symposium, IEEE Computer Society, Denver, p 150Google Scholar
  37. 37.
    Heirman W, Stroobandt D, Miniskar NR, Wuyts R, Catthoor F (2010) PinComm: characterizing intra-application communication for the many-core era. In: Proceedings of the 16th IEEE international conference on parallel and distributed systems (ICPADS), Shanghai, pp 500–507. DOI 101109/ICPADS201056Google Scholar
  38. 38.
    Hemenway R, Grzybowski R, Minkenberg C, Luijten R (2004) Optical-packet-switched interconnect for supercomputer applications. J Opt Netw Special Issue Supercomput Interconnects 3(12):900–913. DOI 101364/JON3000900Google Scholar
  39. 39.
    Henderson CJ, Leyva DG, Wilkinson TD (2006) Free space adaptive optical interconnect at 125  Gb/s, with beam steering using a ferroelectric liquid-crystal SLM. IEEE/OSA J Lightwave Technol 24(5):1989–1997. DOI 101109/JLT2006871015CrossRefGoogle Scholar
  40. 40.
    Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5):51–61. DOI 101109/MM200777CrossRefGoogle Scholar
  41. 41.
    Hu J, Marculescu R (2003) Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. In: Proceedings of the conference on design, automation and test in Europe, pp 688–693. DOI 101109/DATE20031253687Google Scholar
  42. 42.
    Hu J, Marculescu R (2004) Application-specific buffer space allocation for networks-on-chip router design. In: Proceedings of the IEEE/ACM international conference on computer-aided design, San Jose, pp 354–361. DOI 101109/ ICCAD20041382601Google Scholar
  43. 43.
    Jalabert A, Murali S, Benini L, Micheli GD (2004) xPipesCompiler: a tool for instantiating application-specific NoCs. In: Proceedings of the conference on design, automation and test in Europe, vol 2, Paris, pp 884–889. DOI 101109/ DATE20041268999Google Scholar
  44. 44.
    Jerraya A, Wolf W (eds) (2005) Multiprocessor systems-on-chips. Elsevier/Morgan Kaufmann, San FranciscoGoogle Scholar
  45. 45.
    Jha NK (2001) Low power system scheduling and synthesis. In: ICCAD ’01: proceedings of the 2001 IEEE/ACM international conference on computer-aided design, IEEE, Piscataway, pp 259–263 (2001)Google Scholar
  46. 46.
    Kamil S, Pinar A, Gunter D, Lijewski M, Oliker L, Shalf J (2007) Reconfigurable hybrid interconnection for static and dynamic scientific applications. In: Proceedings of the 4th international conference on computing frontiers, ACM, Ischia, pp 183–194. DOI 101145/12425311242559Google Scholar
  47. 47.
    Katsinis C (2001) Performance analysis of the simultaneous optical multi-processor exchange bus. Parallel Comput 27(8):1079–1115CrossRefMATHGoogle Scholar
  48. 48.
    Kodi A, Louri A (2006) RAPID for high-performance computing systems: architecture and performance evaluation. Appl Opt 45:6326–6334CrossRefGoogle Scholar
  49. 49.
    Koohi S, Hessabi S (2009) Contention-free on-chip routing of optical packets. In: Proceedings of the 3rd ACM/IEEE international symposium on networks-on-chip, pp 134–143Google Scholar
  50. 50.
    Krishnamurthy P, Chamberlain R, Franklin M (2003) Dynamic reconfiguration of an optical interconnect. In: Proceedings of the 36th annual simulation symposium, pp 89–97Google Scholar
  51. 51.
    Landman BS, Russo RL (1971) On a pin versus block relationship for partitions of logic graphs. IEEE Trans Comput C-20(12):1469–1479CrossRefGoogle Scholar
  52. 52.
    Lee BG, Biberman A, Chan J, Bergman K (2010) High-performance modulators and switches for silicon photonic networks-on-chip. IEEE J Sel Top Quantum Electron 16(1):6–22. DOI 101109/JSTQE20092028437CrossRefGoogle Scholar
  53. 53.
    Lee BG, Biberman A, Sherwood-Droz N, Poitras CB, Lipson M, Bergman K (2009) High-speed 2 ×2 switch for multiwavelength silicon-photonic networks-on-chip. J Lightwave Technol 27(14):2900–2907CrossRefGoogle Scholar
  54. 54.
    Lee J, Kim D, Ahn H, Park S, Pyo J, Kim G (2007) Temperature-insensitive silicon nano-wire ring resonator. In: Optical fiber communication conference and exposition and the national fiber optic engineers conference, OSA technical digest series (CD), Anaheim, p OWG4Google Scholar
  55. 55.
    Lee SJ, Lee K, Yoo HJ (2005) Analysis and implementation of practical, cost-effective networks on chips. IEEE Design Test Comput 22(5):422–433MathSciNetCrossRefGoogle Scholar
  56. 56.
    Leroy A, Marchal A, Shickova A, Catthoor F, Robert F, Verkest D (2005) Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs. In: Proceedings of the third IEEE/ACM/IFIP International conference on hardware/software codesign and system synthesis, pp 81–86Google Scholar
  57. 57.
    Magnusson PS, Christensson M, Eskilson J, Forsgren D, Hallberg G, Hogberg J, Larsson F, Moestedt A, Werner B (2002) Simics: a full system simulation platform. IEEE Comput 35(2):50–58CrossRefGoogle Scholar
  58. 58.
    McArdle N, Fancey SJ, Dines JAB, Snowdon JF, Ishikawa M, Walker AC (1998) Design of parallel optical highways for interconnecting electronics. Proc SPIE Opt Comput 3490:143–146CrossRefGoogle Scholar
  59. 59.
    McArdle, N, Naruse M, Ishikawa M, Toyoda H, Kobayashi Y (1999) Implementation of a pipelined optoelectronic processor: OCULAR-II. In: Optics in computing, OSA technical digestGoogle Scholar
  60. 60.
    McNutt B (2000) The fractal structure of data reference: applications to the memory hierarchy. Kluwer Academic, Norwell, MA, USAGoogle Scholar
  61. 61.
    Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In: Proceedings of the conference on design, automation and test in Europe, pp 890–895Google Scholar
  62. 62.
    Miniskar NR, Wuyts R, Heirman W, Stroobandt D (2009) Energy efficient resource management for scalable 3D graphics game engine. Tech report, IMECGoogle Scholar
  63. 63.
    Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proceedings of the conference on design, automation and test in Europe, IEEE Computer Society, Washington, p 20896Google Scholar
  64. 64.
    Ogras U, Marculescu R (2006) Prediction-based flow control for network-on-chip traffic. In: Proceedings of the 43rd design automation conference, pp 839–844Google Scholar
  65. 65.
    Ogras UY, Marculescu R (2006) It’s a small world after all’: NoC performance optimization via long-range link insertion. IEEE Trans Very Large Scale Integr Syst Special Sect Hardware/Software Codesign Syst Synth 14(7):693–706. DOI 101109/ TVLSI2006878263. Index terms—Design automation, multiprocessor system-onchip (MP-SoC), network-on-chip (NoC), performance analysisGoogle Scholar
  66. 66.
    Ohashi K, Nishi K, Shimizu T, Nakada M, Fujikata J, Ushida J, Torii S, Nose K, Mizuno M, Yukawa H, Kinoshita M, Suzuki N, Gomyo A, Ishi T, Okamoto D, Furue K, Ueno T, Tsuchizawa T, Watanabe T, Yamada K, Itabashi S, Akedo J (2009) On-chip optical interconnect. Proc IEEE 97(7):1186–1198. DOI 101109/JPROC20092020331CrossRefGoogle Scholar
  67. 67.
    Owens JD, Dally WJ, Ho R, Jayasimha D, Keckler SW, Peh LS (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27(5):96–108CrossRefGoogle Scholar
  68. 68.
    Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54(8): 1025–1040CrossRefGoogle Scholar
  69. 69.
    Parhami B (1999) Introduction to parallel processing: algorithms and architectures. Kluwer AcademicGoogle Scholar
  70. 70.
    Patel R, Bond S, Pocha M, Larson M, Garrett H, Drayton R, Petersen H, Krol D, Deri R, Lowry M (2003) Multiwavelength parallel optical interconnects for massively parallel processing. IEEE J Sel Top Quantum Electron 9:657–666CrossRefGoogle Scholar
  71. 71.
    Petracca M, Lee BG, Bergman K, Carloni LP (2008) Design exploration of optical interconnection networks for chip multiprocessors. In: Proceedings of the 16th IEEE symposium on high performance interconnects, Stanford, pp 31–40. DOI 101109/ HOTI200820Google Scholar
  72. 72.
    Poon AW, Xu F, Luo X (2008) Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip. In: Proceedings of SPIE photonics west, pp 19–24Google Scholar
  73. 73.
    Qiao C, Melhem R, Chiarulli D, Levitan S (1994) Dynamic reconfiguration of optically interconnected networks with time-division multiplexing. J Parallel Distr Comput 22(2):268–278CrossRefGoogle Scholar
  74. 74.
    Roldan R, d’Auroil B (2003) A preliminary feasibility study of the LARPBS optical bus parallel model. In: Proceedings of the 17th annual international symposium on high performance computing systems and applications, pp 181–188Google Scholar
  75. 75.
    Russell G (2004) Analysis and modelling of optically interconnected computing systems. PhD Thesis, Heriot-Watt UniversityGoogle Scholar
  76. 76.
    Sakano T, Matusumoto T, Noguchi K, Sawabe T (1991) Design and performance of a multiprocessor system employing board-to-board free-space interconnections: COSINE-1. Appl Opt 30:2334–2343CrossRefGoogle Scholar
  77. 77.
    Shacham A, Bergman K, Carloni L (2008) Photonic networks-on-chip for future generations of chip multi-processors. IEEE Trans Comput 57(9):1246–1260. DOI 101109/TC200878MathSciNetCrossRefGoogle Scholar
  78. 78.
    Sherwood-Droz N, Wang H, Chen L, Lee BG, Biberman A, Bergman K, Lipson M (2008) Optical 4 ×4 hitless silicon router for optical networks-on-chip (NoC). Opt Express 16(20):15915–15922. DOI 101364/OE16015915CrossRefGoogle Scholar
  79. 79.
    Snyder L (1982) Introduction to the configurable, highly parallel computer. Computer 15(1) :47–56CrossRefGoogle Scholar
  80. 80.
    Soganci IM, Tanemura T, Williams KA, Calabretta N, de Vries T, Smalbrugge E, Smit MK, Dorren HJS, Nakano Y (2010) Monolithically integrated InP 1 ×16 optical switch with wavelength-insensitive operation. IEEE Photon Technol Lett 22(3):143–145CrossRefGoogle Scholar
  81. 81.
    Srinivasan K, Chatha K (2005) A technique for low energy mapping and routing in network-on-chip architectures. In: Proceedings of the international symposium on low power electronics and design, pp 387–392Google Scholar
  82. 82.
    Stensgaard MB, SparsøJ (2008) ReNoC: a network-on-chip architecture with reconfigurable topology. In: 2nd ACM/IEEE international symposium on networks-on-chip, Newcastle, pp 55–64. DOI 101109/NOCS20084492725Google Scholar
  83. 83.
    Stuart MB, Stensgaard MB, SparsøJ (2009) Synthesis of topology configurations and deadlock free routing algorithms for renoc-based systems-on-chip. In: Proceedings of the 7th IEEE/ACM international conference on hardware/software codesign and system synthesis, pp 481–490. DOI 101145/16294351629500Google Scholar
  84. 84.
    Tang S, Tang Y, Colegrove J, Craig DM (2004) Electro-optic Bragg grating couplers for fast reconfigurable optical waveguide interconnects. In: Proceedings of the conference on lasers and electro-optics (CLEO), p 2Google Scholar
  85. 85.
    Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Singh A, Jacob T, Jain S, Erraguntla V, Roberts C, Hoskote Y, Borkar N, Borkar S (2008) An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE J Solid-State Circuits 43(1):29–41 (2008). DOI 101109/JSSC2007910957CrossRefGoogle Scholar
  86. 86.
    Vlasov Y, Green WMJ, Xia F (2008) High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks. Nat Photon 2:242–246CrossRefGoogle Scholar
  87. 87.
    Wolkotte PT, Smit GJM, Rauwerda GK, Smit LT (2005) An energy-efficient reconfigurable circuit-switched network-on-chip. In: Proceedings of the 19th IEEE international parallel and distributed processing symposium (IPDPS), Denver, p 155aGoogle Scholar
  88. 88.
    Woo SC, Ohara M, Torrie E, Singh JP, Gupta A (1995) The SPLASH-2 programs: characterization and methodological considerations. In: Proceedings of the 22nd international symposium on computer architecture, Santa Margherita Ligure, pp 24–36Google Scholar
  89. 89.
    Xu Q, Fattal D, Beausoleil RG (2008) Silicon microring resonators with 15-μm radius. Opt Express 16(6):4309CrossRefGoogle Scholar
  90. 90.
    Yoshimura T, Ojima M, Arai Y, Asama K (2003) Three-dimensional self-organized microoptoelectronic systems for board-level reconfigurable optical interconnects-performance modeling and simulation. IEEE J Sel Top Quantum Electron 9(2):492–511. DOI 101109/JSTQE2003812503CrossRefGoogle Scholar

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© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Computer Systems LaboratoryGhent UniversityGentBelgium
  2. 2.iTEAMUniversidad Politécnica de ValenciaValenciaSpain
  3. 3.Department of Applied Physics and PhotonicsVrije Universiteit BrusselBrusselBelgium

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