Scalable Simulation for MPSoC Software and Architectures

  • Rainer Leupers
  • Stefan Kraemer
  • Lei Gao
  • Christoph Schumacher


Multi-processor systems-on-chip (MPSoCs) are gaining a lot of attraction due to their good performance to power ratio. In order to cope with the complexity of such systems, early availability of full system simulation is of high importance. The simulation time is increasing with the growing number of processors. Therefore, scalable simulation techniques are required to mitigate this problem. Two new concepts to increase the simulation speed are becoming popular. First, raising the abstraction level increases simulation speed at the expense of a lower simulation accuracy. Second, exploiting all available processor cores in today’s host systems increases the simulation speed without sacrificing the accuracy. Depending on the individual use case, one technique alone or a mixture of both techniques can be applied to create a fast simulation environment which is suitable for design space exploration, software development, performance estimation, and debugging.


Performance Estimation Hybrid Simulation Parallel Simulation Design Space Exploration Virtual Simulator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



We thank Pees, Braun, Nohl, Hoffmann, and all the people who have contributed to the development of these techniques [2, 20].


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Copyright information

© Springer Science+business Media, LLC 2010

Authors and Affiliations

  • Rainer Leupers
    • 1
  • Stefan Kraemer
    • 2
  • Lei Gao
    • 2
  • Christoph Schumacher
    • 2
  1. 1.Software for Systems on Silicon (SSS), RWTH Aachen UniversityAachenGermany
  2. 2.RWTH Aachen UniversityAachenGermany

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