Abstract
This chapter presents an approach to accelerating processor simulation using FPGAs. This is distinguished from traditional uses of FPGAs, and the increased development effort from using FPGAs is discussed. Techniques are presented to efficiently control a highly distributed simulation on an FPGA. Time-multiplexing the simulator is presented in order to simulate numerous virtual cores while improving utilization of functional units.
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- 1.
This is 3 instead of 4 because the simulator can perform the first write on the same FPGA cycle as the second read to the synchronous block RAM.
- 2.
There are scenarios in which the FPGA simulator characteristics may give some degree of insight into the corresponding characteristics of the final design. However, this should not be one of the assumptions when using an FPGA for architectural simulation.
- 3.
It should be noted that high-level hardware description languages do not necessarily result in worse FPGA utilization. There are cases where high-level knowledge exposes optimization opportunities [20].
- 4.
Sometimes port-based models contain “false” combinational loops between modules. In this case, a module’s simulation loop must be loosened to correctly handle the false dependencies, as presented in [21].
- 5.
The name A-Ports reflects that they are a generalization of ports in the Asim simulator.
- 6.
This kind of multiplexing bears a resemblance to multi-threading in real microprocessors, but it is important to distinguish that this is a simulator technique, not a technique in the target architecture. The cores being multiplexed do not have to support multi-threading.
- 7.
Again, note that this refers to altering the implementation of the modules on the FPGA, not altering the timing characteristics of the target circuit, which are preserved by the ports.
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Pellauer, M., Adler, M., Parashar, A., Emer, J. (2010). Accelerating Simulation with FPGAs. In: Leupers, R., Temam, O. (eds) Processor and System-on-Chip Simulation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6175-4_7
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