Simulation Acceleration in Wireless Baseband Processing
The Monte Carlo method is state-of-the art to verify the performance of wireless communication systems. Statistical simulations for various signal-to-noise (SNR) operation points are mandatory. Bit error rates (BERs) of 10−9 or even lower require the simulation of tens to hundreds of thousands of blocks for a single SNR operating point. Therefore, system simulation in wireless baseband processing is a challenging task. For example, analyzing the error floor in DVB-S2 LDPC channel-decoding systems needs several weeks of simulation time for one specific set of code parameters. Design validation of hardware architectures is challenging as well for the same reasons. We will present different techniques for accelerating system simulation with emphasis on channel decoding techniques by distributed software simulation , accelerated simulation using the cell processor, and hardware-assisted acceleration using FPGAs . Moreover, we will show how design validation of such systems can be accelerated by rapid prototyping.
KeywordsCheck Node Additive White Gaussian Noise Channel Cell Processor Thread Level Synergistic Processor Element
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