IP Modeling and Verification

  • Emre Özer
  • Nathan Chong
  • Krisztián Flautner


This chapter presents the infrastructure for modeling intellectual property (IP). After a brief introduction to ARM IP and architecture, the modeling and simulation strategies are presented for the RISC CPUs and system-on-chips (SoCs) based on ARM IP. We will explain how the initial investigation of the processor architecture and microarchitecture for performance and power is accomplished before the real design phase. This will be followed by the discussion of different modeling techniques used in the processor design stage such as RTL simulation, emulation, and FPGA prototyping. Then, we will look into the system modeling/simulation frameworks from programmer’s and system designer’s perspectives and discuss their trade-offs. Finally, we will discuss the verification strategies for validating the processor design from ad hoc test techniques, random coverage strategies, assertion-based verification, and formal verification methods.


Intellectual Property Processor Core Register File Pipeline Stage Execution Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+business Media, LLC 2010

Authors and Affiliations

  1. 1.ARM LtdCambridgeUK
  2. 2.ARM LtdCambridgeUK

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