Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors

  • Marc Duranton
  • Jan Hoogerbrugge
  • Ghiath Al-kadi
  • Surendra Guntur
  • Andrei Terechko


Multicore architectures provide scalable performance with a hardware design effort lower than for a single core processor with similar performance. This chapter presents a design methodology and an embedded multicore architecture focusing on boosting performance density and reducing the software design complexity. The methodology is based on a predictive formula computing performance of heterogeneous multicores, which allows drastic pruning of the design space for few accurate simulations. Using this design space exploration methodology for high definition and quad high definition H.264 video decoding, the resulting areas for a multicore system in CMOS 45 nm are 2.5 and 8.6 mm2, respectively. These results show that heterogeneous chip multiprocessors are cost-effective for embedded applications.


Performance Density Clock Frequency Cache Size Hardware Component Data Cache 
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The authors would like to thank Philip Christie and his team for their contribution to this work and the ACOTES project (European project IST-034869) for his valuable contributions to the programming model of the Ne-XVP architecture.


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Copyright information

© Springer Science+business Media, LLC 2010

Authors and Affiliations

  • Marc Duranton
    • 1
  • Jan Hoogerbrugge
    • 2
  • Ghiath Al-kadi
    • 2
  • Surendra Guntur
    • 2
  • Andrei Terechko
    • 3
  1. 1.NXP Semiconductors, Corporate I&T / ResearchEindhovenThe Netherlands
  2. 2.NXP SemiconductorsEindhovenThe Netherlands
  3. 3.Vector Fabrics B.V.EindhovenThe Netherlands

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