On-Chip Busses



The on-chip bus is the backbone of any SoC, and it is a means to efficiently connect various components including processors, memory, and peripherals. The challenges for an on-chip bus are not minor: it has to accommodate a wide range of communication needs with a single, unified architecture. In this chapter we review the key characteristics of the on-chip bus, using several existing on-chip bus standards as examples: ARM/AMBA, IBM/Coreconnect, and Wishbone. We also look at some of the long-term challenges for on-chip interconnect, and how this will affect the design of hardware–software interfaces.


Clock Cycle Timing Diagram Clock Edge 
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  1. IBM (2009) Coreconnect bus architecture. Tech. rep., https://www-01.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect\_Bus\_ArchitectureGoogle Scholar
  2. Micheli GD, Benini L (2006) Networks on Chips: Technology and Tools (Systems on Silicon). Morgan Kaufmann Publishers Inc., San Francisco, CA, USAGoogle Scholar
  3. Pasricha S, Dutt N (2008) On-Chip Communication Architectures: System on Chip Interconnect. Morgan KaufmannGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Bradley Dept. Electrical & Computer EngineeringVirginia TechBlacksburgUSA

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