Stream ciphers are complex state machines that generate an infinite stream of pseudo-random bits starting from a single key. These bits can be used as a keystream in encryption and decryption operations. In this chapter we’ll discuss the implementation of such a stream cipher algorithm, called Trivium, as a co-processor. The co-processor is attached to a host processor. The software on that host processor initializes the Trivium coprocessor, and retrieves a very long (infinite) keystream. We consider different types of host processors, including an 8-bit 8051 microcontroller, a 32-bit StrongARM RISC, and a 32-bit Microblaze processor. We will consider the impact of different types of hardware–software interfaces on the performance of the overall design. We will also investigate the path to implementation on an FPGA.