Advertisement

Pipelined Machines

  • Sandip Ray
Chapter

Abstract

We outline an approach to verify pipelined machines with stuttering trace containment. Pipelined machines are complicated to reason about since they involve simultaneous overlapped execution of different instructions. Nevertheless, we show that if the logic used is sufficiently expressive, then it is possible to relate the executions of the pipelined machine with the corresponding Instruction Set Architecture using (stuttering) simulation. Our methodology uses first-order quantification to define a predicate that relates pipeline states with ISA states and uses its Skolem witness for correspondence proofs. Our methodology can be used to reason about generic pipelines with interrupts, stalls, and exceptions.

Keywords

Register File Program Counter Visible Behavior Simulation Relation Proof Rule 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    M. Aagaard, V. C. Ciubotariu, F. Khalvati, and J. T. Higgins. Combining Equivalence Verification and Completion Functions. In A. J. Hu and A. K. Martin, editors, Proceedings of the 5th International Conference on Formal Methods in Computer-Aided Design (FMCAD 2004), volume 3312 of LNCS, pages 98–112, Austin, TX, November 2004. Springer-Verlag.Google Scholar
  2. 2.
    M. Aagaard, B. Cook, N. Day, and R. B. Jones. A Framework for Microprocessor Correctness Statements. In T. Margaria and T. F. Melham, editors, Proceedings of the 11th International Conference on Correct Hardware Design and Verification Methods (CHARME 2001), volume 2144 of LNCS, pages 443–448, Scotland, UK, 2001. Springer-Verlag.Google Scholar
  3. 31.
    B. Brock and W. A. Hunt, Jr. Formal Analysis of the Motorola CAP DSP. In Industrial-Strength Formal Methods in Practice. Springer, 1999.Google Scholar
  4. 33.
    A. Bronstein and T. L. Talcott. Formal Verification of Pipelines Based on String-Functional Semantics. In L. J. M. Claesen, editor, Formal VLSI Correctness Verification, VLSI Design Methods II, pages 349–366, 1990.Google Scholar
  5. 36.
    R. E. Bryant, S. German, and M. N. Velev. Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions. In N. Halbwachs and D. Peled, editors, Proceedings of the 11th International Conference on Computer-Aided Verification (CAV 1999), volume 1633 of LNCS, pages 470–482, Trendo, Italy, 1999. Springer-Verlag.CrossRefGoogle Scholar
  6. 37.
    R. E. Bryant, S. K. Lahiri, and S. A. Seshia. Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In E. Brinksma and K. G. Larsen, editors, Proceedings of the 14th International Conference on Computer-Aided Verification (CAV 2002), volume 2404 of LNCS, pages 78–92, Copenhagen, Denmark, July 2002. Springer-Verlag.CrossRefGoogle Scholar
  7. 38.
    J. R. Burch and D. L. Dill. Automatic Verification of Pipelined Microprocessor Control. In D. L. Dill, editor, Proceedings of the 6th International Conference on Computer-Aided Verification (CAV 1994), volume 818 of LNCS, pages 68–80, Stanford, CA, 1994. Springer-Verlag.CrossRefGoogle Scholar
  8. 57.
    A. Cohn. A Proof of Correctness of the VIPER Microprocessor. Technical Report 104, University of Cambridge, Computer Laboratory, January 1987.Google Scholar
  9. 107.
    R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying Advanced Microarchitectures that Support Speculation and Exceptions. In E. A. Emerson and A. P. Sistla, editors, Proceedings of the 12th International Conference on Computer-Aided Verification (CAV 2000), volume 1855 of LNCS, Chicago, IL, July 2000. Springer-Verlag.Google Scholar
  10. 108.
    W. A. Hunt, Jr. FM8501: A Verified Microprocessor, volume 795 of LNAI. Springer-Verlag, 1994.Google Scholar
  11. 109.
    W. A. Hunt, Jr. and B. Brock. A Formal HDL and Its Use in the FM9001 Verification. In C. A. R. Hoare and M. J. C. Gordon, editors, Mechanized Reasoning and Hardware Design, Prentice-Hall International Series in Computer Science, pages 35–48, Englewood Cliffs, NJ, 1992. Prentice-Hall.Google Scholar
  12. 115.
    R. Jhala and K. McMillan. Microarchitecture Verification by Compositional Model Checking. In G. Berry, H. Comon, and A. Finkel, editors, Proceedings of 12th International Conference on Computer-Aided Verification (CAV), volume 2102 of LNCS, Paris, France, 2001. Springer-Verlag.Google Scholar
  13. 136.
    S. K. Lahiri and R. E. Bryant. Deductive Verification of Advanced Out-of-Order Microprocessors. In W. A. Hunt, Jr. and F. Somenzi, editors, Proceedings of the 15th International Conference on Computer-Aided Verification (CAV 2003), volume 2275 of LNCS, pages 341–354, Boulder, CO, July 2003. Springer-Verlag.CrossRefGoogle Scholar
  14. 150.
    P. Manolios. Correctness of Pipelined Machines. In W. A. Hunt, Jr. and S. D. Johnson, editors, Proceedings of the 3rd International Conference on Formal Methods in Computer-Aided Design (FMCAD 2000), volume 1954 of LNCS, pages 161–178, Austin, TX, 2000. Springer-Verlag.Google Scholar
  15. 152.
    P. Manolios. A Compositional Theory of Refinement for Branching Time. In D. Geist, editor, Proceedings of the 12th Working Conference on Correct Hardware Design and Verification Methods, volume 2860 of LNCS, pages 304–218, L‘Aquila, Italy, 2003. Springer-Verlag.Google Scholar
  16. 155.
    P. Manolios and S. Srinivasan. Automatic Verification of Safety and Liveness of XScale-Like Processor Models Using WEB Refinements. In Design, Automation and Test in Europe (DATE 2004), pages 168–175, Paris, France, 2004. IEEE Computer Society Press.Google Scholar
  17. 156.
    P. Manolios and S. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. In Design, Automation and Test in Europe (DATE 2005), pages 1304–1309, Munich, Germany, 2005. IEEE Computer Society Press.CrossRefGoogle Scholar
  18. 210.
    S. Ray and W. A. Hunt, Jr. Deductive Verification of Pipelined Machines Using First-Order Quantification. In R. Alur and D. A. Peled, editors, Proceedings of the 16th International Conference on Computer-Aided Verification (CAV 2004), volume 3114 of LNCS, pages 31–43, Boston, MA, July 2004. Springer-Verlag.CrossRefGoogle Scholar
  19. 226.
    J. Sawada. Verification of a Simple Pipelined Machine Model. In M. Kaufmann, P. Manolios, and J. S. Moore, editors, Computer-Aided Reasoning: ACL2 Case Studies, pages 35–53, Boston, MA, June 2000. Kluwer Academic Publishers.Google Scholar
  20. 227.
    J. Sawada and W. A. Hunt, Jr. Trace Table Based Approach for Pipelined Microprocessor Verification. In O. Grumberg, editor, Proceedings of the 9th International Conference on Computer-Aided Verification (CAV 1997), volume 1254 of LNCS, pages 364–375, Haifa, Israel, 1997. Springer-Verlag.CrossRefGoogle Scholar
  21. 228.
    J. Sawada and W. A. Hunt, Jr. Processor Verification with Precise Exceptions and Speculative Execution. In A. J. Hu and M. Y. Vardi, editors, Proceedings of the 10th International Conference on Computer-Aided Verification (CAV 1998), volume 1427 of LNCS, pages 135–146, Vancouver, BC, 1998.Springer-Verlag.Google Scholar
  22. 229.
    J. Sawada and W. A. Hunt, Jr. Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability. Formal Methods in Systems Design, 20(2):187–222, 2002.MATHCrossRefGoogle Scholar
  23. 241.
    M. Srivas and M. Bickford. Formal Verification of a Pipelined Microprocessor. IEEE Software, 7(5):52–64, September 1990.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Department of Computer SciencesUniversity of Texas, AustinAustinUSA

Personalised recommendations