Ensuring correct and reliable behavior of a modern computing system implementation is a challenging exercise. Formal verification offers one approach to address the challenge, for example, the use of mathematical analysis to prove that a system satisfies its desired property or specification. Formal verification has achieved significant success in the analysis of specific design components, such as the floating-point unit of a modern microprocessor. Nevertheless, there is still a significant gap between the ability of the state-of-the-art in formal verification today and the capacity required for analysis of a modern computing system.


Decision Procedure Theorem Prover Deductive Reasoning Formal Verification Sequential Program 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 9.
    F. Baader and T. Nipkow. Term Rewriting and All that. Cambridge University Press, 1998.Google Scholar
  2. 28.
    R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. A. Edwards, S. P. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa. VIS: A System for Verification and Synthesis. In R. Alur and T. Henzinger, editors, Proceedings of the 8th International Conference on Computer-Aided Verification (CAV 1996), volume 1102 of LNCS, pages 428–432, New Brunswick, NJ, July 1996. Springer-Verlag.CrossRefGoogle Scholar
  3. 32.
    B. Brock, M. Kaufmann, and J. S. Moore. ACL2 Theorems About Commercial Microprocessors. In M. Srivas and A. Camilleri, editors, Proceedings of the 1st International Conference on Formal Methods in Computer-Aided Design (FMCAD 1996), volume 1166 of LNCS, pages 275–293, Palo Alto, CA, 1996. Springer-Verlag.CrossRefGoogle Scholar
  4. 44.
    C. Chou. The Mathematical Foundation of Symbolic Trajectory Evaluation. In N. Halbwacha and D. Peled, editors, Proceedings of the 11th International Conference on Computer-Aided Verification (CAV 1999), volume 1633 of LNCS, pages 196–207, Trendo, Italy, 1999. Springer-Verlag.CrossRefGoogle Scholar
  5. 49.
    E. M. Clarke and E. A. Emerson. Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic. In D. C. Kozen, editor, Logic of Programs, Workshop, volume 131 of LNCS, pages 52–71, Yorktown Heights, NY, May 1981. Springer-Verlag.Google Scholar
  6. 88.
    M. J. C. Gordon and T. F. Melham, editors. Introduction to HOL: A Theorem-Proving Environment for Higher-Order Logic. Cambridge University Press, 1993.MATHGoogle Scholar
  7. 90.
    S. Graf and H. Saidi. Construction of Abstract State Graphs with PVS. In O. Grumberg, editor, Proceedings of the 9th International Conference on Computer-Aided Verification (CAV 1997), volume 1254 of LNCS, pages 72–83, Haifa, Israel, 1997. Springer-Verlag.CrossRefGoogle Scholar
  8. 100.
    J. Harrison. The HOL Light Manual Version 1.1. Technical Report, University of Cambridge Computer Laboratory, New Museums Site, Pembroke Street, Cambridge CB2 3Qg, England, April 2000. See URL
  9. 116.
    R. B. Jones. Symbolic Simulation Methods for Industrial Formal Verification. Kluwer Academic Publishers, June 2002.CrossRefGoogle Scholar
  10. 121.
    M. Kaufmann, P. Manolios, and J. S. Moore, editors. Computer-Aided Reasoning: ACL2 Case Studies. Kluwer Academic Publishers, Boston, MA, June 2000.Google Scholar
  11. 122.
    M. Kaufmann, P. Manolios, and J. S. Moore. Computer-Aided Reasoning: An Approach. Kluwer Academic Publishers, Boston, MA, June 2000.Google Scholar
  12. 165.
    K. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.Google Scholar
  13. 171.
    P. Molitor and J. Mohnke. Equivalence Checking of Digital Circuits: Fundamentals, Principles, Methods. Springer-Verlag, 2004.Google Scholar
  14. 179.
    J. S. Moore, T. Lynch, and M. Kaufmann. A Mechanically Checked Proof of the Kernel of the AMD5K86 Floating-Point Division Algorithm. IEEE Transactions on Computers, 47(9):913–926, September 1998.MathSciNetCrossRefGoogle Scholar
  15. 189.
    T. Nipkow, L. Paulson, and M. Wenzel. Isabelle/HOL: A Proof Assistant for Higher Order Logics, volume 2283 of LNCS. Springer-Verlag, 2002.Google Scholar
  16. 191.
    J. O’Leary, X. Zhao, R. Gerth, and C. H. Seger. Formally Verifying IEEE Compliance of Floating-Point Hardware. Intel Technology Journal, Q1-1999, 1999.Google Scholar
  17. 194.
    S. Owre, J. M. Rushby, and N. Shankar. PVS: A Prototype Verification System. In D. Kapoor, editor, 11th International Conference on Automated Deduction (CADE), volume 607 of LNAI, pages 748–752. Springer-Verlag, June 1992.Google Scholar
  18. 206.
    President’s Information Technology Advisory Committee. Information Technology Research: Investing in Our Future, February 1999. National Coordination Office for Computing, Information, and Communications. See URL
  19. 207.
    J. P. Queille and J. Sifakis. Specification and Verification of Concurrent Systems in CESAR. In Proceedings of the 5th International Symposimum on Programming, volume 137 of LNCS, pages 337–351, Colloquium is ter instead of symposium, Torino, Italy, 1982. Springer-Verlag.Google Scholar
  20. 223.
    D. Russinoff. A Mechanically Checked Proof of IEEE Compliance of a Register-Transfer-Level Specification of the AMD-K7 Floating-Point Multiplication, Division, and Square Root Instructions. LMS Journal of Computation and Mathematics, 1:148–200, December 1998.MathSciNetMATHCrossRefGoogle Scholar
  21. 242.
    G. L Steele, Jr. Common Lisp the Language. Digital Press, 30 North Avenue, Burlington, MA 01803, 2nd edition, 1990.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Department of Computer SciencesUniversity of Texas, AustinAustinUSA

Personalised recommendations