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IC-Package-System Integration Design

  • Yiyu Shi
  • Yang Shang
  • Hao Yu
  • Shauki Elassaad
Chapter

Abstract

Miniature is massive when it comes to electronics. While there exists a continuous effort in industry to integrate more functionalities into the same area, the prohibitive scaling cost at 45nm and beyond makes it difficult to continue the trend. Towards this, More-than-Moore techniques have been proposed, which explore new dimensionality of integration by creating and integrating non-digital functionality to semiconductor products (Zhang and Roosmalen. More than Moore—creating hnanoelectronics systems/nanoelectronics systems. Springer, New York, 2009). They motivate new technological possibilities and unlimited application potential.

In order to achieve integration of complete electrical functional blocks within a package, integrated chip-package-system (ICPS) solution has emerged as a cost-effective and flexible solution for More-than-Moore. High-volume commercial and consumer applications are benefiting from the integration of multiple semiconductor devices with other passive and active components within a conventional IC package. The near future of IC packaging includes the integration of MEMS, optical, and photonic devices into subsystems including semiconductors. Package proliferation is the direct result of the demands being placed on the traditional IC package by evolution of device and system technology. As applications become more demanding, packaging technology expands to deliver the optimal solution at the lowest cost.

For integrated device manufacturer (IDM), while system on a chip (SOC) will continue to be a focus area, more applications are taking advantage of package-level integration to deliver complete subsystems to their customers. For example, wafer-fabrication mask costs, short product lives, and relatively low-yielding, mixed-technology wafer-fabrication processes make SOC undesirable for some applications. The emerging ICPS applications solve these problems by assembling multiple devices into a single IC package. Logic and memory combinations are prevalent. The logic device can be combined with various memory capacities to customize the packaged product for different applications.

In radio frequency (RF) applications, where passive network design is critical to complete the subsystem design, the ICPS solution can move this complexity off the system board and into the package. This approach is becoming common for wireless applications, where standard radio components can be used to deliver wireless connectivity to a variety of end-products without the need to have extensive RF design capability.

Three-dimensional packaging is an approach that is gaining wide acceptance for space-constrained ICPS applications. Stacking silicon dies inside a package allows multiple device types to be integrated into the same space as a single die. The vast majority of mobile phones produced today employ this technology. FLASH and SRAM memories are commonly stacked inside a single package. Going forward, the move to 2.5 and 3G cell-phone functionality will requires a higher level of integration. Many companies will integrate the digital base band processor device and potentially other ASICs for functionality, such as MP3 decoding and GPS processing, into stacked configurations with increased capacity memory device.

As for semiconductor assembly and test services (SATS), they are following common solutions: Chip Scale Packaging (CSP) provides chip manufacturers with design options to address the various physical form factor and performance needs of their products. Enabling a variety of package types including lead bonded, wire bonded, and various multi-chip package solutions, the current CSP technology satisfies performance, size, and reliability requirements across a wide range of applications. Multi-Chip Packaging includes technologies for die stacking, mixed die System-in-Package (SiP), and Package-on-Package (PoP) stacking through substrate folding and by ball stacking. Flip-Chip Packaging provides a solution for high yield and reliability for high-performance high I/O devices. The flip-chip interconnect offers inherent advantages for high performance from increased interconnect density in a smaller area. Flip-Chip Interconnect is a scalable, copper interconnect technology addressing the industries need for ever-finer pitch flip-chip solutions with larger die, ultra low-K dielectrics, and lead-free materials.

Increased package-level integration creates a number of new challenges since various silicon devices in a single package may not come from the same semiconductor company. New levels of cooperation are required between semiconductor companies, packaging companies, and end users to develop an efficient design flow that allows efficient implementation of integrated designs and maintains a fair yield. Design automation and verification of various components within a packaged system needs to be considered and the appropriate level of capability designed into the system.

Current gaps in the ICPS tool flow include multilevel constraint management, multi-technology tool support, multi-domain simulation support, multilevel models and verifications. In addition, a standard data format between IC package and printed circuit board (PCB) design tools is also required. For example, there is no single design flow with a tool to handle electrical, mechanical, and thermal concerns across the chip, package, and board. Moreover, the flow requires the consideration of electrostatic discharge (ESD), wire-loop optimization for multiple die stacks, as well as new tools to support emerging through-silicon-via (TSV) technologies in three-dimensional packaging.

The chapter is organized as follows. Section8.1 offers a general overview of the design explorations and considerations to tackle the above problems. Section8.2 zooms into the topic of decoupling capacitor insertion for noise suppression, and Section8.3 discusses the three-dimensional integrated systems, an emerging technique for More-than-Moore.

Keywords

Clock Signal Power Integrity Legal Position Area Overhead Impedance Matrix 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

Some works in this chapter are supported in part by the University of Missouri Research Board (UMRB). The authors would also like to express their great gratitude to the editors for their hard work, and to the anonymous reviewers for their constructive comments, which led to considerable improvements in the technical content.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Missouri University of Science and Technology (formerly University of Missouri, Rolla)RollaUSA
  2. 2.Nanyang Technological UniversitySingaporeSingapore
  3. 3.Stanford UniversityStanfordUSA

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