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Technology/Circuit Co-Design for III-V FETs

  • Jaydeep P. Kulkarni
  • Kaushik Roy
Chapter

Abstract

III-V semiconductor based Field Effect Transistors (FET) are conceived as a promising candidate for low voltage high performance applications. In this chapter, we show the complete technology-circuit assessment of III-V FETs. The co-design approach spans from the device/SPICE models, logic/memory circuit analysis to technology requirements. We show feasibility of the use of Si + III-V hybrid technology for future high speed low voltage applications. We prescribe the technology requirements as well as suggest the application space for III-V FETs.

Keywords

Schottky Diode Noise Margin Sleep Transistor Sheet Carrier Density Power Delay Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

The authors would like to thank Prof. Muhammad. A. Alam, Prof. Mark Lundstrom, Prof. Supriyo Datta, Prof. Peter Ye, Prof. Ram Mohan, Prof. Trond Ytterdal, Prof. Suman Datta, Dr. Vivek De, Shekhar Borkar and Dr. Robert Chau for useful technical discussions. This research was funded in part by Semiconductor Research Corporation (SRC) and by Intel Foundation Ph.D. Fellowship Award.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.School of Electrical and Computer Engineering, Purdue UniversityW. LafayetteUSA

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