Technology/Circuit Co-Design for III-V FETs

  • Jaydeep P. Kulkarni
  • Kaushik Roy


III-V semiconductor based Field Effect Transistors (FET) are conceived as a promising candidate for low voltage high performance applications. In this chapter, we show the complete technology-circuit assessment of III-V FETs. The co-design approach spans from the device/SPICE models, logic/memory circuit analysis to technology requirements. We show feasibility of the use of Si + III-V hybrid technology for future high speed low voltage applications. We prescribe the technology requirements as well as suggest the application space for III-V FETs.


Schottky Diode Noise Margin Sleep Transistor Sheet Carrier Density Power Delay Product 
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The authors would like to thank Prof. Muhammad. A. Alam, Prof. Mark Lundstrom, Prof. Supriyo Datta, Prof. Peter Ye, Prof. Ram Mohan, Prof. Trond Ytterdal, Prof. Suman Datta, Dr. Vivek De, Shekhar Borkar and Dr. Robert Chau for useful technical discussions. This research was funded in part by Semiconductor Research Corporation (SRC) and by Intel Foundation Ph.D. Fellowship Award.


  1. 1.
    De V. and Borkar. S.; Technology and Design Challenges for Low Power and High Performance, Proceedings of International Symposium on Low Power Electronics and design, 163–168 (1999)Google Scholar
  2. 2.
    Roy K. and Prasad S.; Low Power VLSI Circuit Design, Wiley (2000)Google Scholar
  3. 3.
    Bohr M.T.; Nanotechnology Goals and Challenges for Electronic Applications, IEEE Transactions on Nanotechnology, Vol. 1, No. 1, 56–62 (2002)CrossRefGoogle Scholar
  4. 4.
    Chau R., Datta R. and Majumdar A.; Opprtunities and Challenges of III-V Nanoelectronics for Future High Speed, Low Power Logic Applications, Proceedings of Compound Semiconductor Integrated Circuit Symposium, 17–20 (2005)Google Scholar
  5. 5.
    Vurgaftman I., Meyer J. R., Ram-Mohan L. R.; Band Parameters for III-V Compound Semiconductors and their Alloys, Journal of Applied Physics, Vol. 89, 5815–5875 (2001)CrossRefGoogle Scholar
  6. 6.
    Madelung O.; Semiconductor Data Handbook, Springer-Verlag, 3rd edition, New York (2003)Google Scholar
  7. 7.
    Levinshtein M., Rumyantsev S. and Shur M.; Handbook Series on Semiconductor Parameters, New Jersey: World Scientific, Singapore (1996)CrossRefGoogle Scholar
  8. 8.
    Singh J.; Physics of Semiconductors and Their Hetero-structures, McGraw-Hill, Inc., New York (1993) Google Scholar
  9. 9.
    Datta S., Ashley T., Brask J., Buckle J., Doczy M., Emeny M., Hayes D., Hilton K., Jefferies R., Martin T., Phillips T. J., Wallis D., Wilding P. and Chau. R.; 85 nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications, Proceedings of International Electron Device Meeting, 763–766 (2005) Google Scholar
  10. 10.
    Kulkarni J. P. and Roy K.; Technology Circuit Co-Design for Ultra Fast InSb Quantum Well Transistors, IEEE Transactions on Electron Devices, Vol. 55, No. 10, 2537–2545 (2008) CrossRefGoogle Scholar
  11. 11.
    Krishnamohan T., Krivokapic Z., Uchida K., Nishi Y. and Saraswat K. C.; Low Defect Ultrathin Fully Strained-Ge MOSFET on Relaxed Si with High Mobility and Low Band-to-Band-Tunneling (BTBT), Proceedings of VLSI Technology Symposium, 82–83 (2005) Google Scholar
  12. 12.
    Sze S. M., High Speed Semiconductor Device, Willey-Interscience, 1st Edition (1990)Google Scholar
  13. 13.
    Lee K., Shur M., Fjeldly T. A. and Ytterdal T.; Semiconductor Device Modeling for VLSI, Prentice Hall Inc, New Jersey (1993) Google Scholar
  14. 14.
    Byun Y., Lee K. and Shur M.; Unified Charge Control Model and Subthreshold Current in Heterostructure Field Effect Transistors, IEEE Electron Device Letters, Vol. EDL-11, 50–53 (1990) CrossRefGoogle Scholar
  15. 15.
    Meyer J. E.; MOS Models and Circuit Simulation, RCA Review, Vol. 32, 42–63 (1971) Google Scholar
  16. 16.
    Long S. I. and Butner S. E.; Gallium Arsenide Digital Integrated Circuit Design, New York: McGraw-Hill (1990)Google Scholar
  17. 17.
    Chau R., Brask J., Datta S., Dewey G., Doczy M., Doyle B., Kavalieros J., Jin B., Metz M., Majumdar A. and Radosavljevic M.; Application of High-k Gate Dielectrics and Metal Gate Electrodes to Enable Silicon and Non-silicon Logic Nanotechnology, Microelectronics Engineering, Vol. 80, 1–6 (2005)CrossRefGoogle Scholar
  18. 18.
    Zhao W. and Cao Y.; New Generation of Predictive Technology Model for Sub-45nm Design Exploration, Proceedings of International Symposium on Quality Electronics Design, 585–590 (2006)Google Scholar
  19. 19.
    Predictive Technology Models: Available online at
  20. 20.
    Karnik T., Ye Y., Tschanz J., Wei L., Burns S., Govindarajulu V., De V. and Borkar S.; Total Power Optimization by Simultaneous Dual-V T Allocation and Device Sizing in High Performance Microprocessors, Proceedings of 39th Design Automation Conference, 486–491 (2002) Google Scholar
  21. 21.
    Ashley T., Buckle L., Datta S., Emeny M.T., Hayes D.G., Hilton K.P., Jefferies R., Martin T., Phillips T.J., Wallis D.J., Wilding P.J. and Chau R.; Heterogeneous InSb Quantum Well Transistors on Silicon for Ultra-High Speed, Low Power Logic Applications, Electronics Letters, Vol. 43, No.14 (2007)CrossRefGoogle Scholar
  22. 22.
    Hudait M. K., Datta S., Dewey G., Fastenau J. M., Kavalieros J., Liu W. K., Lubyshev D., Pillarisetty, R., Radosavljevic M. and Chau R.; Heterogeneous Integration of Enhancement Mode In0:7Ga0:3 As Quantum Well Transistor on Silicon Substrate using Thin (<2 µm) Composite Buffer Architecture for High-Speed and Low-voltage (0.5 V) Logic Applications, Proceedings of International Electron Device Meeting, 625–628 (2007)Google Scholar
  23. 23.
    Yoshinobu N., Masahi H., Takayuki K. and Itoh K.; Review and Future Prospects of Low-Voltage RAM Circuits, IBM Journal of Research and Development, Vol. 47, No. 5/6, 525–552 (2003) Google Scholar
  24. 24.
    Seevinck E., List F. and Lohstroh J., Static Noise Margin Analysis of MOS SRAM Cells, IEEE Journal Solid-State Circuits, Vol. SC-22, No. 5, pp. 748–754 (1987) CrossRefGoogle Scholar
  25. 25.
    Chandrakasan A. and Bowhill W., Fox F., Design of High Performance Microprocessor Circuits, 1st edition, Wiley-IEEE press (2000) Google Scholar
  26. 26.
    Khare M., Ku S. H., Donaton R. A., Greco S., Brodsky C., Chen X., Chou A., DellaGuardia R., Deshpande S., Doris B., Fung S. K. H., Gabor A., Gribelyuk M., Holmes S., Jamin F. F., Lai W. L., Lee W. H., Li Y., McFarland P., Mo R., Mittl S., Narasimha S., Nielsen D., Purtell R., Rausch W., Sankaran S., Snare J., Tsou L., Vayshenker A., Wagner T., Wehella-Gamage D., Wu E., Wu S., Yan W., Barth E., Ferguson R., Gilbert P., Schepis D., Sekiguchi A., Goldblatt R.,Welser J., Muller K. P. and Agnello P., A High Performance 90 nm SOI Technology with 0.992 µm 2 6T-SRAM Cell, Proceedings of International Electron Device Meeting, 407–410 (2002)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.School of Electrical and Computer Engineering, Purdue UniversityW. LafayetteUSA

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