Abstract
The performance of nano-CMOS digital ICs is characterized in terms of key figure of merits, which provides a benchmark for III-V compound semiconductor MOSFETs. The selection of III-V channel material is discussed based on the transport properties, i.e., the intrinsic electron mobility and hole mobility, of different III-V alloys. To improve the hole mobility for III-V p-MOSFETs, the effects of strain-induced hole mobility enhancement are reviewed. Critical process issues for self-aligned III-V MOSFET are thermal stability of the oxide-semiconductor interface and source/drain doping limitations. The advantages of self-aligned GaAs enhancement-mode MOSFETs using regrown source and drain regions are demonstrated. Finally, the state-of-the-art device performance of sub-100 nm gate III-V FETs is compared with Si MOSFETs.
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References
M. Hong, J. N. Baillargeon, J. Kwo, J. P. Mannaerts, and A. Y. Cho, “First demonstration of GaAs CMOS,” Proceedings of 2000 IEEE International Symposium on Compound Semiconductors, 2000, p. 345.
M. Bohr, “MOS transistors: Scaling and performance trends,” Semiconductor International, June 1995, pp. 75–80.
S. Natarajan et al., “A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and SRAM cell size in a 291 Mb array,” IEDM Tech. Dig., 2008, pp. 1–3.
B. Doyle et al., “Transistor elements for 30 nm physical gate length and beyond,” Intel Technol. J., 6, 42 (2002).
J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, “Subbreakdown drain leakage current in MOSFET,” IEEE Electron Device Lett., 8, 515 (1987).
R. Chau et al., “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans. Nanotechnol., 4, 153 (2005).
Sadao Adachi, Properties of group-IV, III-V and II-VI semiconductors, (John Wiley & Sons, 2005), p. 322.
D. Chattopadhyay, S. K. Sutradhar, and B. R. Nag, “Electron transport in direct-gap III-V ternary alloys,” J. Phys. C, 14, 891 (1981).
H. Miki, K. Segawa, M. Otsubo, K. Shirahata, and K. Fujibayashi, “Growth of InxGa1−xSb by liquid phase epitaxy,” in GaAs and Related Compounds (Inst. Phys. Conf. Ser. no. 24, Inst. of Phys., London and Bristol, 1975), pp. 16–21.
M. Kawashima and S. Kataoka, “Electron velocity-field characteristics of GaxIn1−xSb measured by a microwave heating technique,” Jpn. J. Appl. Phys., 18, 1311 (1979).
S. E. Thompson et al., “A 90 nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, 51, 1790 (2004).
M. L. Lee and E. A. Fitzgerald, “Hole mobility enhancements in nanometer-scale strained-silicon structures grown on Ge-rich relaxed Si1−xGex,” J. Appl. Phys., 94, 2590 (2003).
Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., 101, 104503 (2007).
S. L. Chuang, “Efficient band-structure calculations of strained quantum wells,” Phys. Rev. B, 43, 9649 (1991).
S. Datta et al., “85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications,” IEDM Tech. Dig., 2005, pp. 763–766.
M. Radosavljevic et al., “High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC = 0.5 V) logic applications,” IEDM Tech. Dig., 2008, pp. 1–4.
R. Chau, S. Datta, and A. Majumdar, “Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications,” IEEE Compound Semiconductor Integrated Circuit Symposium, 2005, pp. 17–20.
H. W. Kennel et al., “Kinetics of shallow junction activation: Physical mechanism,” Proceedings International Conference on Advanced Thermal Processing, 2006, pp. 85–91.
D. Cheng, C. Liao, K. Y. Cheng, and M. Feng, “Process development and characteristics of nano III-V MOSFET,” International Conference on Compound Semiconductor Manufacturing Technology (CS MANTECH) Technology Digest, 2008, pp. 339–342.
C. Liao, D. Cheng, C. Cheng, K. Y. Cheng, M. Feng, T. H. Chiang, J. Kwo, and M. Hong, “Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts,” J. Crystal Growth, 311, 1958 (2009).
D. Barlage et al., “Low temperature selected area regrowth of ohmic contacts for III-N FETs,” Mater. Res. Soc. Symp., 892, (2006).
P. D. Ye, “Main determinants for III-V metal-oxide-semiconductor field-effect-transistors,” J. Vac. Sci. Technol. A, 26, 697 (2008).
T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W. Tsai, and Y. C. Wang, “High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3/Ga2O3(Gd2O3) as gate dielectrics,” Appl. Phys. Lett., 93, 033516 (2008).
Y. Xuan, Y. Q. Wu, and P. D. Ye, “High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm,” IEEE Electron Device Lett., 29, 294 (2008).
Y. Q. Wu, W. K. Wang, O. Koybasi, D. N. Zakharov, E. A. Stach, S. Nakahara, J. C. M. Hwang, and P. D. Ye, “0.8 V supply voltage deep-submicrometer inversion-mode In0.75Ga0.25As MOSFET,” IEEE Electron Device Lett., 30, 700 (2009).
C. H. Jan et al., “A 65 nm ultra low power logic platform technology using uni-axial strained silicon transistors,” IEDM Tech. Dig., 2007, pp. 60–63.
N. Waldron, D. Kim, and J. A. Alamo, “90 nm self-aligned enhancement-mode InGaAs HEMT for logic applications,” IEDM Tech. Dig., 2007, pp. 633–636.
D. Kim and J. A. Alamo, “30 nm E-mode InAs pHEMTs for THz and future logic applications,” IEDM Tech. Dig., 2008, pp. 830–833.
M. Hudait et al., “Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications,” IEDM Tech. Dig., 2007, pp. 625–628.
S. Datta, “III-V field-effect transistors for low power digital logic applications,” Microelectronic Eng., 84, 2133 (2007).
Y. Sun et al., "High-performance In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics and α-Si passivation,” IEEE Electron Device Lett., 30, 5 (2009).
R. Yan, A. Ourmazd, and K, Lee, “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans Electron Dev., 39, 1704 (1992).
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This work is supported in part by the MARCO MSD Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program.
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Cheng, K., Feng, M., Cheng, D., Liao, C. (2010). Sub-100 nm Gate III-V MOSFET for Digital Applications. In: Oktyabrsky, S., Ye, P. (eds) Fundamentals of III-V Semiconductor MOSFETs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-1547-4_10
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DOI: https://doi.org/10.1007/978-1-4419-1547-4_10
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