Electrochemical Fabrication Process for ULSI Interconnects

Part of the Nanostructure Science and Technology book series (NST)


In the field of ultra-large-scale integration (ULSI) technologies, electrodeposited copper (Cu) has been used since 1997 as the interconnection material [1, 2]. Recently, most manufacturers have switched over to electrodeposited Cu interconnect technology. Before the introduction of electrodeposited Cu to interconnects, Al and/or Al–Cu alloys were used. The Al interconnects are easily fabricated by the subtractive etching process. In this process, the Al layers are deposited by physical vapor deposition (PVD), followed by reactive ion etching (RIE). Al is preferable for interconnects because this material does not diffuse into the SiO2 substrate and the layers adhere well to the substrate (Fig. 15.1 a). However, resistivity of Al is relatively high (2.65 μΩ cm), and the layers suffer from the disadvantage of its poor electromigration resistance. With an increase in the density of interconnects and a decrease in the dimensions of interconnects, the problem of an increase in latency, or RC delay, and electromigraion become much more critical. Therefore, the search for new interconnect materials enabling a further miniaturization of semiconductor devices has mainly focused on minimizing RC delay and electromigration [3–10]. Cu has been regarded as a potential candidate for an interconnection material because of its lower resistivity (1.68 μΩ cm) compared with that of Al. The other important advantage of Cu interconnects is that Cu offers much better electromigration resistance than Al does. At a comparable dimension, the time-to-failure of a Cu interconnect was about a 100 times as long as that of an Al one [11–13]. Therefore, Cu interconnection is able to support higher current density, and this makes it possible to accelerate further miniaturization of interconnects. The Cu interconnection technologies were originally developed through the implementation of the “Damascene process” introduced by IBM (Fig. 15.1 b) [1, 2].


Barrier Layer Sheet Resistance Deposition Potential Electroless Plating Electroless Deposition 
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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Faculty of Science and EngineeringWaseda UniversityShinjuku-kuJapan

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