Electrochemical Fabrication Process for ULSI Interconnects

  • Tetsuya Osaka
  • Masahiro Yoshino
Part of the Nanostructure Science and Technology book series (NST)


In the field of ultra-large-scale integration (ULSI) technologies, electrodeposited copper (Cu) has been used since 1997 as the interconnection material [1, 2]. Recently, most manufacturers have switched over to electrodeposited Cu interconnect technology. Before the introduction of electrodeposited Cu to interconnects, Al and/or Al–Cu alloys were used. The Al interconnects are easily fabricated by the subtractive etching process. In this process, the Al layers are deposited by physical vapor deposition (PVD), followed by reactive ion etching (RIE). Al is preferable for interconnects because this material does not diffuse into the SiO2 substrate and the layers adhere well to the substrate (Fig. 15.1 a). However, resistivity of Al is relatively high (2.65 μΩ cm), and the layers suffer from the disadvantage of its poor electromigration resistance. With an increase in the density of interconnects and a decrease in the dimensions of interconnects, the problem of an increase in latency, or RC delay, and electromigraion become much more critical. Therefore, the search for new interconnect materials enabling a further miniaturization of semiconductor devices has mainly focused on minimizing RC delay and electromigration [3–10]. Cu has been regarded as a potential candidate for an interconnection material because of its lower resistivity (1.68 μΩ cm) compared with that of Al. The other important advantage of Cu interconnects is that Cu offers much better electromigration resistance than Al does. At a comparable dimension, the time-to-failure of a Cu interconnect was about a 100 times as long as that of an Al one [11–13]. Therefore, Cu interconnection is able to support higher current density, and this makes it possible to accelerate further miniaturization of interconnects. The Cu interconnection technologies were originally developed through the implementation of the “Damascene process” introduced by IBM (Fig. 15.1 b) [1, 2].


Barrier Layer Sheet Resistance Deposition Potential Electroless Plating Electroless Deposition 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Andricacos PC, Uzoh C et al (1998) Damascene copper electroplating for chip interconnections. IBM J Res Dev 42:567–574CrossRefGoogle Scholar
  2. 2.
    Andricacos PC (1999) Copper on-chip interconnections a breakthrough in electrodeposition to make better chips. Electrochem Soc Interface 8:32–37Google Scholar
  3. 3.
    Ismail YI, Friedman EG et al (2001) Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 9:963–973CrossRefGoogle Scholar
  4. 4.
    Deutsch A, Kopcsay GV et al (2001) Frequency-dependent losses on high-performance interconnections. IEEE Trans Electromagn Compat 43:446–465CrossRefGoogle Scholar
  5. 5.
    Ismail YI et al (2001) Repeater insertion in tree structured inductive interconnect. IEEE Trans Circuits Syst II – Analog Digit Signal Process 48:471–481CrossRefGoogle Scholar
  6. 6.
    Deutsch A et al (2001) On-chip wiring design challenges for gigahertz operation. Proc IEEE 89:529–555CrossRefGoogle Scholar
  7. 7.
    Ismail YI, Friedman EG et al (2000) Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 8:195–206CrossRefGoogle Scholar
  8. 8.
    Ismail YI et al (2000) Equivalent Elmore delay for RLC trees. IEEE Trans CAD Integr Circuits Syst 19:83–97CrossRefGoogle Scholar
  9. 9.
    Sakurai T (1983) Approximation of wiring delay in MOSFET LSI. IEEE J Solid-State Circuit 18:418–426CrossRefGoogle Scholar
  10. 10.
    Edelstein DC et al (1995) VLSI on-chip interconnection performance simulations and measurements. IBM J Res Dev 39:383–402CrossRefGoogle Scholar
  11. 11.
    Edelstein DC et al (1997) Full copper wiring in a sub-0.25 μm CMOS ULSI technology. In: Technical digest IEEE international electron devices meeting, 773–776Google Scholar
  12. 12.
    Venkatesan S et al (1997) A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization. In: Technological digest, IEEE international electron devices meeting, 769–772Google Scholar
  13. 13.
    Rosenberg R et al (2000) Copper metallization for high performance silicon technology. Annu Rev Mat Sci 30:229–262CrossRefGoogle Scholar
  14. 14.
    Suntola T (1984) Atomic Layer Epitaxy. 16th international conference on solid state devices and materials, 647–650Google Scholar
  15. 15.
    Suntola T, Antson J US patent No. 4058430Google Scholar
  16. 16.
    Ritala M, Leskelä M (2002) Deposition and processing of thin films. In: Nalwa HS (ed) Handbook of thin film materials, volume 1. Academic, San DiegoGoogle Scholar
  17. 17.
    Suntola T (1992) Atomic layer epitazy. Thin Solid Films 216:84–89CrossRefGoogle Scholar
  18. 18.
    Shacham Diamand Y, Lopatin S (1997) High aspect ratio quarter-micron electroless copper integrated technology. Microelectron Eng 37(38):77–88CrossRefGoogle Scholar
  19. 19.
    Shacham Diamand Y, Lopatin S (1999) Integrated electroless metallization for ULSI. Electrochim Acta 44:3639–3649CrossRefGoogle Scholar
  20. 20.
    Shacham Diamand Y, Sverdlov Y (2000) Electrochemically deposited thin film alloys for ULSI and MEMS applications. Microelectron Eng 50:525–531CrossRefGoogle Scholar
  21. 21.
    O’Sullivan EJ et al (1998) Electrolessly deposited diffusion barriers for microelectronics. IBM J Res Dev 42:607–620CrossRefGoogle Scholar
  22. 22.
    Osaka T et al (2002) Fabrication of electroless NiReP barrier layer on SiO2 without sputtered seed layer. J Electrochem Solid-State Lett 5:C7–C10CrossRefGoogle Scholar
  23. 23.
    Osaka T et al (2002) Electroless nickel ternary alloy deposition on SiO2 for application to diffusion barrier layer in copper interconnect technology. J Electrochem Soc 149:C573–C578CrossRefGoogle Scholar
  24. 24.
    Osaka T et al (2003) Characterization of chemically-deposited NiB and NiWB thin films as a capping layer for ULSI application. Surf Coat Technol 169(170):124–127CrossRefGoogle Scholar
  25. 25.
    Osaka T et al (2004) Formation of high functional thin films in electronics. J Surf Fin Soc Jpn 55:753–757CrossRefGoogle Scholar
  26. 26.
    Yoshino M et al (2005) All-wet fabrication process for ULSI interconnect technologies. Electrochim Acta 51:916–920CrossRefGoogle Scholar
  27. 27.
    Yoshino M et al (2006) Fabrication of the electroless NiMoB films as a diffusion barrier layer on the low-k substrate. ECS Trans 1:57–67CrossRefGoogle Scholar
  28. 28.
    Osaka T et al (2003) Microfabrication of electro- and electroless-deposition and it application in the electronic field. Surf Coat Technol 169(170):1–7CrossRefGoogle Scholar
  29. 29.
    Kind H et al (1998) Electroless deposition of metal nanoislands on aminothiolate-functionalized Au(111) electrodes. J Phys Chem B 102:7582–7589CrossRefGoogle Scholar
  30. 30.
    Hasegawa M et al (2007) Evidence for “superfilling” of submicrometer trenches with electroless copper deposit. Appl Phys Lett 90:101916CrossRefGoogle Scholar
  31. 31.
    Shingubara S et al (2004) Bottom-up fill of copper in deep submicrometer holes by electroless plating. Electrochem Solid-State Lett 7:C78–C80CrossRefGoogle Scholar
  32. 32.
    Shimada K et al (2005) Precise measurement of the self-diffusion coefficient for poly(ethylene glycol) in aqueous solution using uniform oligomers. J Chem Phys 122:244914CrossRefGoogle Scholar
  33. 33.
    Norkus E, Vaskelis A (1987) Russ J Inorg Chem 32:130Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Faculty of Science and EngineeringWaseda UniversityShinjuku-kuJapan

Personalised recommendations