SIMD Optimization

  • Manuel Hohenauer
  • Rainer Leupers


As concluded in the previous chapter, retargetable compilers, as used in ASIP design environments, are still hampered by their limited code quality as compared to hand-written compilers or assembly code. Consequently, generated compilers must be manually refined to a highly optimizing compiler after successful architecture exploration. One way of overcoming this dilemma is to design retargetable optimizations for those architectural features that characterize a class of target processors.


Scalar Expansion Code Size Strip Mining Loop Body Embed Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.RWTH Aachen University Institute for Software for Systems on SiliconAachenGermany

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