The complexity of today’s SoC designs is increasing at an exponential rate due to the combined effects of advances in semiconductor technology as well as demands from increasingly complex applications in embedded systems. Escalating NRE costs have created a shift toward achieving greater design reuse with programmable SoC platforms. The choice of programmable architectures strongly affects the success of a SoC design due to its impact on the overall cost, power consumption, and performance. Therefore, an increasing number of embedded SoC designs employ ASIPs as building blocks due to their balance between flexibility and high performance by programmability and application-specific optimizations. However, given today’s tight time-to-market constraints, finding the optimal balance between competing
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