Abstract
2D wave type topographic operators are distributed into six classes, based on their implementation methods on different low-power many-core architectures. The following architectures are considered: (1) pipe-line architecture, (2) coarse-grain cellular parallel architecture, (3) fine-grain fully parallel cellular architecture with discrete time processing, (4) fine-grain fully parallel cellular architecture with continuous time processing, and (5) DSP-memory architecture as a reference. Efficient implementation methods of the classes are shown on each architecture. The processor utilization efficiencies, as well as the execution times, and the major constrains are calculated. On the basis of the calculated parameters, an optimal architecture can be selected for a given algorithm.
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The minimal value of the pixels clock is equivalent to the product of the frame-rate and the number of pixels (resolution). If the image source is a sensor, the pixel clock is defined by the sensor readout speed. In balanced sensor applications (high-speed applications are usually balanced), the integration time and the readout time are roughly the same. Since there are short blank periods in the sensor readout protocol for synchronization purposes, the pixel clock is slightly higher then the minimal pixel clock in balanced application. However, in low light applications, the sensor integration time takes much longer than the readout time. In these cases, the sensor pixel clock can be orders of magnitude higher than the minimal pixel clock.
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Zarándy, Á., Rekeczky, C. (2010). Low-Power Processor Array Design Strategy for Solving Computationally Intensive 2D Topographic Problems. In: Baatar, C., Porod, W., Roska, T. (eds) Cellular Nanoscale Sensory Wave Computing. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-1011-0_10
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