Low-Power Processor Array Design Strategy for Solving Computationally Intensive 2D Topographic Problems



2D wave type topographic operators are distributed into six classes, based on their implementation methods on different low-power many-core architectures. The following architectures are considered: (1) pipe-line architecture, (2) coarse-grain cellular parallel architecture, (3) fine-grain fully parallel cellular architecture with discrete time processing, (4) fine-grain fully parallel cellular architecture with continuous time processing, and (5) DSP-memory architecture as a reference. Efficient implementation methods of the classes are shown on each architecture. The processor utilization efficiencies, as well as the execution times, and the major constrains are calculated. On the basis of the calculated parameters, an optimal architecture can be selected for a given algorithm.


Wave Front Clock Cycle Processor Utilization Processor Array Readout Time 
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  1. Chua L O and Yang L, “Cellular neural networks: theory and applications”, IEEE Transactions on Circuits and Systems, vol. 35, no. 10, October 1988, pp. 1257–1290.Google Scholar
  2. Chua L O, Roska T, Kozek T, Zarándy Á, “CNN universal chips crank up the computing power”, IEEE Circuits and Devices, July 1996, pp. 18–28.Google Scholar
  3. Cruz J M, Chua L O, Roska T, “A fast, complex and efficient test implementation of the CNN universal machine”, Proc. of the third IEEE Int. Workshop on Cellular Neural Networks and their Application (CNNA-94), pp. 61-66, Rome Dec. 1994.Google Scholar
  4. Dudek P, and Carey S J, “A general-purpose 128 ×128 SIMD processor array with integrated image sensor”, Electronics Letters, vol. 42, no. 12, June 2006, pp. 678–679.Google Scholar
  5. Dudek P, “An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 53 no. 5, 2006 pp. 354–358.Google Scholar
  6. Espejo S, Carmona R, Domínguez-Castro R, Rodríguez-Vázquez, A, “A VLSI-oriented continuous-time CNN model”, International Journal of Circuit Theory and Applications, vol. 24, May–June 1996, pp. 341–356.Google Scholar
  7. Espejo S, Carmona R, Domingúez-Castro R, Rodrigúez-Vázquez A, “CNN universal chip in CMOS technology”, Int. J. of Circuit Theory & Appl., vol. 24, 1996, pp. 93–111.Google Scholar
  8. Foldesy P, Zarándy Á, Rekeczky Cs, Roska T, “Configurable 3D integrated focal-plane sensor-processor array architecture”, Int. J. Circuit Theory and Applications (CTA), 2008, pp. 573–588.Google Scholar
  9. Harrer H, Nossek J A, Roska T, Chua L O, “A Current-mode DTCNN Universal Chip”, Proc. of IEEE Intl. Symposium on Circuits and Systems, 1994, pp. 135–138.Google Scholar
  10. Kahle J A, Day M N, Hofstee H P, Johns C R, Maeurer T R, Shippy D, “Introduction to the Cell multiprocessor”, IBM J. Res. & Dev., vol. 49, no. 4/5, July/September 2005.Google Scholar
  11. Keresztes P, Zarándy Á, Roska T, Szolgay P, Bezák T, Hídvégi T, Jónás P, Katona A, “An emulated digital CNN implementation”, Journal of VLSI Signal Processing Special Issue: Spatiotemporal Signal Processing with Analogic CNN Visual Microprocessors, (JVSP Special Issue), Kluwer, 1999 November–December.Google Scholar
  12. Liñan-Cembrano G, Rodríguez-Vázquez A, Espejo-Meana S, Domínguez-Castro R, “ACE16k: A 128 ×128 focal plane analog processor with digital I/O”, International Journal of Neural System, vol. 13, no. 6, 2003, pp. 427–434.Google Scholar
  13. Lopich, Dudek P, “Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array”, ECCTD 2007, Seville, Spain.Google Scholar
  14. Nagy Z, and Szolgay P, “Configurable Multi-Layer CNN-UM Emulator on FPGA”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, 2003, pp. 774–778.Google Scholar
  15. Paasio A, Dawindzuk, Halonen K, Porra V, “Minimum size 0.5 micron CMOS programmable 48 ×48 CNN test chip”, European Conference on Circuit Theory and Design, Budapest, 1997, pp. 154–115.Google Scholar
  16. Rekeczky C S, and Chua L O, “Computing with front propagation: active contour and skeleton models in continuous-time CNN”, Journal of VLSI Signal Processing Systems, Vol. 23, No. 2/3, November-December 1999, pp. 373–402.Google Scholar
  17. Roska T and Chua L O, “The CNN universal machine: an analogic array computer”, IEEE Transactions on Circuits and Systems - II, vol. 40, March 1993, pp. 163–173.Google Scholar
  18. Roska T, Kék L, Nemes L, Zarándy Á, Brendel M, Szolgay P, “CNN Software Library (Templates and Algorithms) Version 7.2”, (DNS-1-1998), Budapest, MTA SZTAKI, 1998,
  19. Zarándy Á, “The art of CNN template design”, Int. J. Circuit Theory and Applications - Special Issue: Theory, Design and Applications of Cellular Neural Networks: Part II: Design and Applications, (CTA Special Issue - II), Vol. 17, No. 1, 1999, pp. 5–24.Google Scholar
  20. Zarándy Á, Keresztes P, Roska T, Szolgay P, “CASTLE: An emulated digital architecture; design issues, new results”, Proceedings of 5th IEEE International Conference on Electronics, Circuits and Systems, (ICECS’98), Vol. 1, 1998, pp. 199–202, Lisboa.Google Scholar

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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Computer and Automation Research Institute of the Hungarian Academy of SciencesBudapestHungary
  2. 2.Eutecus Inc.BerkeleyCalifornia

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